List of semiconductor scale examples

The following is a list of semiconductor scale examples for various MOSFET (metal–oxide–semiconductor field-effect transistor, or MOS transistor) semiconductor manufacturing process nodes.

Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
Future

Timeline of MOSFET demonstrations
See also: MOSFET, Semiconductor device fabrication, and Transistor density

PMOS and NMOS
MOSFET (PMOS and NMOS) demonstrations
Date Channel length Oxide thickness[1] MOSFET logic Researcher(s) Organization Ref
June 1960 20,000 nm 100 nm PMOS Mohamed M. Atalla, Dawon Kahng Bell Telephone Laboratories [2][3]
NMOS
10,000 nm 100 nm PMOS Mohamed M. Atalla, Dawon Kahng Bell Telephone Laboratories [4]
NMOS
May 1965 8,000 nm 150 nm NMOS Chih-Tang Sah, Otto Leistiko, A.S. Grove Fairchild Semiconductor [5]
5,000 nm 170 nm PMOS
December 1972 1,000 nm ? PMOS Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu IBM T.J. Watson Research Center [6][7][8]
1973 7,500 nm ? NMOS Sohichi Suzuki NEC [9][10]
6,000 nm ? PMOS ? Toshiba [11][12]
October 1974 1,000 nm 35 nm NMOS Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu IBM T.J. Watson Research Center [13]
500 nm
September 1975 1,500 nm 20 nm NMOS Ryoichi Hori, Hiroo Masuda, Osamu Minato Hitachi [7][14]
March 1976 3,000 nm ? NMOS ? Intel [15]
April 1979 1,000 nm 25 nm NMOS William R. Hunter, L. M. Ephrath, Alice Cramer IBM T.J. Watson Research Center [16]
December 1984 100 nm 5 nm NMOS Toshio Kobayashi, Seiji Horiguchi, K. Kiuchi Nippon Telegraph and Telephone [17]
December 1985 150 nm 2.5 nm NMOS Toshio Kobayashi, Seiji Horiguchi, M. Miyake, M. Oda Nippon Telegraph and Telephone [18]
75 nm ? NMOS Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis MIT [19]
January 1986 60 nm ? NMOS Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis MIT [20]
June 1987 200 nm 3.5 nm PMOS Toshio Kobayashi, M. Miyake, K. Deguchi Nippon Telegraph and Telephone [21]
December 1993 40 nm ? NMOS Mizuki Ono, Masanobu Saito, Takashi Yoshitomi Toshiba [22]
September 1996 16 nm ? PMOS Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [23]
June 1998 50 nm 1.3 nm NMOS Khaled Z. Ahmed, Effiong E. Ibok, Miryeong Song Advanced Micro Devices (AMD) [24][25]
December 2002 6 nm ? PMOS Bruce Doris, Omer Dokumaci, Meikei Ieong IBM [26][27][28]
December 2003 3 nm ? PMOS Hitoshi Wakabayashi, Shigeharu Yamagami NEC [29][27]
NMOS

CMOS (single-gate)
Complementary MOSFET (CMOS) demonstrations (single-gate)
Date Channel length Oxide thickness[1] Researcher(s) Organization Ref
February 1963 ? ? Chih-Tang Sah, Frank Wanlass Fairchild Semiconductor [30][31]
1968 20,000 nm 100 nm ? RCA Laboratories [32]
1970 10,000 nm 100 nm ? RCA Laboratories [32]
December 1976 2,000 nm ? A. Aitken, R.G. Poulsen, A.T.P. MacArthur, J.J. White Mitel Semiconductor [33]
February 1978 3,000 nm ? Toshiaki Masuhara, Osamu Minato, Toshio Sasaki, Yoshio Sakai Hitachi Central Research Laboratory [34][35][36]
February 1983 1,200 nm 25 nm R.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. Pelley Intel [37][38]
900 nm 15 nm Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima Nippon Telegraph and Telephone (NTT) [37][39]
December 1983 1,000 nm 22.5 nm G.J. Hu, Yuan Taur, Robert H. Dennard, Chung-Yu Ting IBM T.J. Watson Research Center [40]
February 1987 800 nm 17 nm T. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige Hirano Matsushita [37][41]
700 nm 12 nm Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima Nippon Telegraph and Telephone (NTT) [37][42]
September 1987 500 nm 12.5 nm Hussein I. Hanafi, Robert H. Dennard, Yuan Taur, Nadim F. Haddad IBM T.J. Watson Research Center [43]
December 1987 250 nm ? Naoki Kasai, Nobuhiro Endo, Hiroshi Kitajima NEC [44]
February 1988 400 nm 10 nm M. Inoue, H. Kotani, T. Yamada, Hiroyuki Yamauchi Matsushita [37][45]
December 1990 100 nm ? Ghavam G. Shahidi, Bijan Davari, Yuan Taur, James D. Warnock IBM T.J. Watson Research Center [46]
1993 350 nm ? ? Sony [47]
1996 150 nm ? ? Mitsubishi Electric
1998 180 nm ? ? TSMC [48]
December 2003 5 nm ? Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki Ikezawa NEC [29][49]

Multi-gate MOSFET (MuGFET)
Multi-gate MOSFET (MuGFET) demonstrations
Date Channel length MuGFET type Researcher(s) Organization Ref
August 1984 ? DGMOS Toshihiro Sekigawa, Yutaka Hayashi Electrotechnical Laboratory (ETL) [50]
1987 2,000 nm DGMOS Toshihiro Sekigawa Electrotechnical Laboratory (ETL) [51]
December 1988 250 nm DGMOS Bijan Davari, Wen-Hsing Chang, Matthew R. Wordeman, C.S. Oh IBM T.J. Watson Research Center [52][53]
180 nm
? GAAFET Fujio Masuoka, Hiroshi Takato, Kazumasa Sunouchi, N. Okabe Toshiba [54][55][56]
December 1989 200 nm FinFET Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji Takeda Hitachi Central Research Laboratory [57][58][59]
December 1998 17 nm FinFET Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor University of California (Berkeley) [60][61]
2001 15 nm FinFET Chenming Hu, Yang‐Kyu Choi, Nick Lindert, Tsu-Jae King Liu University of California (Berkeley) [60][62]
December 2002 10 nm FinFET Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor University of California (Berkeley) [60][63]
June 2006 3 nm GAAFET Hyunjin Lee, Yang-kyu Choi, Lee-Eun Yu, Seong-Wan Ryu KAIST [64][65]

Other types of MOSFET
MOSFET demonstrations (other types)
Date Channel length Oxide thickness[1] MOSFET type Researcher(s) Organization Ref
October 1962 ? ? TFT Paul K. Weimer RCA Laboratories [66][67]
1965 ? ? GaAs H. Becke, R. Hall, J. White RCA Laboratories [68]
October 1966 100,000 nm 100 nm TFT T.P. Brody, H.E. Kunig Westinghouse Electric [69][70]
August 1967 ? ? FGMOS Dawon Kahng, Simon Min Sze Bell Telephone Laboratories [71]
October 1967 ? ? MNOS H.A. Richard Wegener, A.J. Lincoln, H.C. Pao Sperry Corporation [72]
July 1968 ? ? BiMOS Hung-Chang Lin, Ramachandra R. Iyer Westinghouse Electric [73][74]
October 1968 ? ? BiCMOS Hung-Chang Lin, Ramachandra R. Iyer, C.T. Ho Westinghouse Electric [75][74]
1969 ? ? VMOS ? Hitachi [76][77]
September 1969 ? ? DMOS Y. Tarui, Y. Hayashi, Toshihiro Sekigawa Electrotechnical Laboratory (ETL) [78][79]
October 1970 ? ? ISFET Piet Bergveld University of Twente [80][81]
October 1970 1,000 nm ? DMOS Y. Tarui, Y. Hayashi, Toshihiro Sekigawa Electrotechnical Laboratory (ETL) [82]
1977 ? ? VDMOS John Louis Moll HP Labs [76]
? ? LDMOS ? Hitachi [83]
July 1979 ? ? IGBT Bantval Jayant Baliga, Margaret Lazeri General Electric [84]
December 1984 2,000 nm ? BiCMOS H. Higuchi, Goro Kitsukawa, Takahide Ikeda, Y. Nishio Hitachi [85]
May 1985 300 nm ? ? K. Deguchi, Kazuhiko Komatsu, M. Miyake, H. Namatsu Nippon Telegraph and Telephone [86]
February 1985 1,000 nm ? BiCMOS H. Momose, Hideki Shibata, S. Saitoh, Jun-ichi Miyamoto Toshiba [87]
November 1986 90 nm 8.3 nm ? Han-Sheng Lee, L.C. Puzio General Motors [88]
December 1986 60 nm ? ? Ghavam G. Shahidi, Dimitri A. Antoniadis, Henry I. Smith MIT [89][20]
May 1987 ? 10 nm ? Bijan Davari, Chung-Yu Ting, Kie Y. Ahn, S. Basavaiah IBM T.J. Watson Research Center [90]
December 1987 800 nm ? BiCMOS Robert H. Havemann, R. E. Eklund, Hiep V. Tran Texas Instruments [91]
June 1997 30 nm ? EJ-MOSFET Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [92]
1998 32 nm ? ? ? NEC [27]
1999 8 nm
April 2000 8 nm ? EJ-MOSFET Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [93]

Commercial products using micro-scale MOSFETs

Products featuring 20 μm manufacturing process

Products featuring 10 μm manufacturing process

Products featuring 8 μm manufacturing process

Products featuring 6 μm manufacturing process

Products featuring 3 μm manufacturing process

Products featuring 1.5 μm manufacturing process

Products featuring 1 μm manufacturing process

Products featuring 800 nm manufacturing process

Products featuring 600 nm manufacturing process
  • Mitsubishi Electric, Toshiba and NEC introduced 16 Mb DRAM memory chips manufactured with a 600 nm process in 1989.[47]
  • NEC's 16 Mb EPROM memory chip in 1990.[47]
  • Mitsubishi's 16 Mb flash memory chip in 1991.[47]
  • Intel 80486DX4 CPU launched in 1994.
  • IBM/Motorola PowerPC 601, the first PowerPC chip, was produced in 0.6 μm.
  • Intel Pentium CPUs at 75 MHz, 90 MHz and 100 MHz.

Products featuring 350 nm manufacturing process

Products featuring 250 nm manufacturing process

Processors using 180 nm manufacturing technology

Processors using 130 nm manufacturing technology
  • Fujitsu SPARC64 V - 2001[101]
  • Gekko by IBM and Nintendo (GameCube console) - 2001
  • Motorola PowerPC 7447 and 7457 - 2002
  • IBM PowerPC G5 970 - October 2002 - June 2003
  • Intel Pentium III Tualatin and Coppermine - 2001-04
  • Intel Celeron Tualatin-256 - 2001-10-02
  • Intel Pentium M Banias - 2003-03-12
  • Intel Pentium 4 Northwood- 2002-01-07
  • Intel Celeron Northwood-128 - 2002-09-18
  • Intel Xeon Prestonia and Gallatin - 2002-02-25
  • VIA C3 - 2001
  • AMD Athlon XP Thoroughbred, Thorton, and Barton
  • AMD Athlon MP Thoroughbred - 2002-08-27
  • AMD Athlon XP-M Thoroughbred, Barton, and Dublin
  • AMD Duron Applebred - 2003-08-21
  • AMD K7 Sempron Thoroughbred-B, Thorton, and Barton - 2004-07-28
  • AMD K8 Sempron Paris - 2004-07-28
  • AMD Athlon 64 Clawhammer and Newcastle - 2003-09-23
  • AMD Opteron Sledgehammer - 2003-06-30
  • Elbrus 2000 1891ВМ4Я (1891VM4YA) - 2008-04-27
  • MCST-R500S 1891BM3 - 2008-07-27
  • Vortex 86SX -

Commercial products using nano-scale MOSFETs
See also: Nanoelectronics and Nanocircuitry

Chips using 90 nm manufacturing technology
  • Sony/Toshiba Emotion Engine+Graphics Synthesizer (PlayStation 2) - 2003[102]
  • IBM PowerPC G5 970FX - 2004
  • Elpida Memory's 90 nm DDR2 SDRAM process - 2005
  • IBM PowerPC G5 970MP - 2005
  • IBM PowerPC G5 970GX - 2005
  • IBM "Waternoose" Xbox 360 Processor - 2005
  • IBM/Sony/ Toshiba Cell Processor - 2005
  • Intel Pentium 4 Prescott - 2004-02
  • Intel Celeron D Prescott-256 - 2004-05
  • Intel Pentium M Dothan - 2004-05
  • Intel Celeron M Dothan-1024 - 2004-08
  • Intel Xeon Nocona, Irwindale, Cranford, Potomac, Paxville - 2004-06
  • Intel Pentium D Smithfield - 2005-05
  • AMD Athlon 64 Winchester, Venice, San Diego, Orleans - 2004-10
  • AMD Athlon 64 X2 Manchester, Toledo, Windsor - 2005-05
  • AMD Sempron Palermo and Manila - 2004-08
  • AMD Turion 64 Lancaster and Richmond - 2005-03
  • AMD Turion 64 X2 Taylor and Trinidad - 2006-05
  • AMD Opteron Venus, Troy, and Athens - 2005-08
  • AMD Dual-core Opteron Denmark, Italy, Egypt, Santa Ana, and Santa Rosa
  • VIA C7 - 2005-05
  • Loongson (Godson) 2Е STLS2E02 - 2007-04
  • Loongson (Godson) 2F STLS2F02 - 2008-07
  • MCST-4R - 2010-12
  • Elbrus-2C+ - 2011-11

Processors using 65 nm manufacturing technology
  • Sony/Toshiba EE+GS (PStwo)[103] - 2005
  • Intel Pentium 4 (Cedar Mill) – 2006-01-16
  • Intel Pentium D 900-series – 2006-01-16
  • Intel Celeron D (Cedar Mill cores) – 2006-05-28
  • Intel Core – 2006-01-05
  • Intel Core 2 – 2006-07-27
  • Intel Xeon (Sossaman) – 2006-03-14
  • AMD Athlon 64 series (starting from Lima) – 2007-02-20
  • AMD Turion 64 X2 series (starting from Tyler)- 2007-05-07
  • AMD Phenom series
  • IBM's Cell Processor – PlayStation 3 – 2007-11-17
  • IBM's z10
  • Microsoft Xbox 360 "Falcon" CPU – 2007–09
  • Microsoft Xbox 360 "Opus" CPU – 2008
  • Microsoft Xbox 360 "Jasper" CPU – 2008–10
  • Microsoft Xbox 360 "Jasper" GPU – 2008–10
  • Sun UltraSPARC T2 – 2007–10
  • AMD Turion Ultra – 2008-06[104]
  • TI OMAP 3 Family[105] – 2008-02
  • VIA Nano – 2008-05
  • Loongson – 2009
  • NVIDIA GeForce 8800GT GPU - 2007

Processors using 45 nm technology

Chips using 32 nm technology
  • Toshiba produced commercial 32 Gb NAND flash memory chips with the 32 nm process in 2009.[107]
  • Intel Core i3 and i5 processors, released in January 2010[108]
  • Intel 6-core processor, codenamed Gulftown[109]
  • Intel i7-970, was released in late July 2010, priced at approximately US$900
  • AMD FX Series processors, codenamed Zambezi and based on AMD's Bulldozer architecture, were released in October 2011. The technology utilised a 32 nm SOI process, two CPU cores per module, and up to four modules, ranging from a quad-core design costing approximately US$130 to a $280 eight-core design.
  • Ambarella Inc. announced the availability of the A7L system-on-a-chip circuit for digital still cameras, providing 1080p60 high-definition video capabilities in September 2011[110]

Chips using 26–24 nm technology
  • Hynix Semiconductor announced that it could produce a 26 nm flash chip with 64 Gb capacity; Intel Corp. and Micron Technology had by then already developed the technology themselves. Announced in 2010.[111]
  • Toshiba announced that it was shipping 24 nm flash memory NAND devices on August 31, 2010.[112]

Chips using 22 nm technology
  • Intel Core i7 and Intel Core i5 processors based on Intel's Ivy Bridge 22 nm technology for series 7 chip-sets went on sale worldwide on April 23, 2012.[113]

Chips using 20 nm technology

Chips using 16 nm technology

Chips using 14 nm technology
  • Intel Core i7 and Intel Core i5 processors based on Intel's Broadwell 14 nm technology was launched in January 2015.[116]
  • AMD Ryzen processors based on AMD's Zen or Zen+ architectures and which utilizes 14 nm FinFET technology.[117]

Chips using 10 nm technology

Chips using 7 nm technology
  • TSMC began risk production of 256 Mbit SRAM memory chips using a 7 nm process in April 2017.[123]
  • Samsung and TSMC began mass production of 7 nm devices in 2018.[124]
  • Apple A12 and Huawei Kirin 980 mobile processors, both released in 2018, use 7 nm chips manufactured by TSMC.[125]

Chips using 5 nm technology
  • Samsung began production of 5 nm chips (5LPE) in late 2018.[126]
  • TSMC began production of 5 nm chips (CLN5FF) in April 2019.[127]

3 nm technology

See also

References
  1. "Angstrom". Collins English Dictionary. Retrieved 2019-03-02.
  2. Sze, Simon M. (2002). Semiconductor Devices: Physics and Technology (PDF) (2nd ed.). Wiley. p. 4. ISBN 0-471-33372-7.
  3. Atalla, Mohamed M.; Kahng, Dawon (June 1960). "Silicon–silicon dioxide field induced surface devices". IRE-AIEE Solid State Device Research Conference. Carnegie Mellon University Press.
  4. Voinigescu, Sorin (2013). High-Frequency Integrated Circuits. Cambridge University Press. p. 164. ISBN 9780521873024.
  5. Sah, Chih-Tang; Leistiko, Otto; Grove, A. S. (May 1965). "Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces". IEEE Transactions on Electron Devices. 12 (5): 248–254. Bibcode:1965ITED...12..248L. doi:10.1109/T-ED.1965.15489.
  6. Dennard, Robert H.; Gaensslen, Fritz H.; Yu, Hwa-Nien; Kuhn, L. (December 1972). "Design of micron MOS switching devices". 1972 International Electron Devices Meeting: 168–170. doi:10.1109/IEDM.1972.249198.
  7. Hori, Ryoichi; Masuda, Hiroo; Minato, Osamu; Nishimatsu, Shigeru; Sato, Kikuji; Kubo, Masaharu (September 1975). "Short Channel MOS-IC Based on Accurate Two Dimensional Device Design". Japanese Journal of Applied Physics. 15 (S1): 193. doi:10.7567/JJAPS.15S1.193. ISSN 1347-4065.
  8. Critchlow, D. L. (2007). "Recollections on MOSFET Scaling". IEEE Solid-State Circuits Society Newsletter. 12 (1): 19–22. doi:10.1109/N-SSC.2007.4785536.
  9. "1970s: Development and evolution of microprocessors" (PDF). Semiconductor History Museum of Japan. Retrieved 27 June 2019.
  10. "NEC 751 (uCOM-4)". The Antique Chip Collector's Page. Archived from the original on 2011-05-25. Retrieved 2010-06-11.
  11. "1973: 12-bit engine-control microprocessor (Toshiba)" (PDF). Semiconductor History Museum of Japan. Retrieved 27 June 2019.
  12. Belzer, Jack; Holzman, Albert G.; Kent, Allen (1978). Encyclopedia of Computer Science and Technology: Volume 10 - Linear and Matrix Algebra to Microorganisms: Computer-Assisted Identification. CRC Press. p. 402. ISBN 9780824722609.
  13. Dennard, Robert H.; Gaensslen, F. H.; Yu, Hwa-Nien; Rideout, V. L.; Bassous, E.; LeBlanc, A. R. (October 1974). "Design of ion-implanted MOSFET's with very small physical dimensions" (PDF). IEEE Journal of Solid-State Circuits. 9 (5): 256–268. Bibcode:1974IJSSC...9..256D. CiteSeerX 10.1.1.334.2417. doi:10.1109/JSSC.1974.1050511.
  14. Kubo, Masaharu; Hori, Ryoichi; Minato, Osamu; Sato, Kikuji (February 1976). "A threshold voltage controlling circuit for short channel MOS integrated circuits". 1976 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XIX: 54–55. doi:10.1109/ISSCC.1976.1155515.
  15. "Intel Microprocessor Quick Reference Guide". Intel. Retrieved 27 June 2019.
  16. Hunter, William R.; Ephrath, L. M.; Cramer, Alice; Grobman, W. D.; Osburn, C. M.; Crowder, B. L.; Luhn, H. E. (April 1979). "1 /spl mu/m MOSFET VLSI technology. V. A single-level polysilicon technology using electron-beam lithography". IEEE Journal of Solid-State Circuits. 14 (2): 275–281. doi:10.1109/JSSC.1979.1051174.
  17. Kobayashi, Toshio; Horiguchi, Seiji; Kiuchi, K. (December 1984). "Deep-submicron MOSFET characteristics with 5 nm gate oxide". 1984 International Electron Devices Meeting: 414–417. doi:10.1109/IEDM.1984.190738.
  18. Kobayashi, Toshio; Horiguchi, Seiji; Miyake, M.; Oda, M.; Kiuchi, K. (December 1985). "Extremely high transconductance (above 500 mS/mm) MOSFET with 2.5 nm gate oxide". 1985 International Electron Devices Meeting: 761–763. doi:10.1109/IEDM.1985.191088.
  19. Chou, Stephen Y.; Antoniadis, Dimitri A.; Smith, Henry I. (December 1985). "Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon". IEEE Electron Device Letters. 6 (12): 665–667. Bibcode:1985IEDL....6..665C. doi:10.1109/EDL.1985.26267.
  20. Chou, Stephen Y.; Smith, Henry I.; Antoniadis, Dimitri A. (January 1986). "Sub‐100‐nm channel‐length transistors fabricated using x‐ray lithography". Journal of Vacuum Science & Technology B: Microelectronics Processing and Phenomena. 4 (1): 253–255. Bibcode:1986JVSTB...4..253C. doi:10.1116/1.583451. ISSN 0734-211X.
  21. Kobayashi, Toshio; Miyake, M.; Deguchi, K.; Kimizuka, M.; Horiguchi, Seiji; Kiuchi, K. (1987). "Subhalf-micrometer p-channel MOSFET's with 3.5-nm gate Oxide fabricated using X-ray lithography". IEEE Electron Device Letters. 8 (6): 266–268. Bibcode:1987IEDL....8..266M. doi:10.1109/EDL.1987.26625.
  22. Ono, Mizuki; Saito, Masanobu; Yoshitomi, Takashi; Fiegna, Claudio; Ohguro, Tatsuya; Iwai, Hiroshi (December 1993). "Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions". Proceedings of IEEE International Electron Devices Meeting: 119–122. doi:10.1109/IEDM.1993.347385. ISBN 0-7803-1450-6.
  23. Kawaura, Hisao; Sakamoto, Toshitsugu; Baba, Toshio; Ochiai, Yukinori; Fujita, Jun'ichi; Matsui, Shinji; Sone, Jun'ichi (1997). "Proposal of Pseudo Source and Drain MOSFETs for Evaluating 10-nm Gate MOSFETs". Japanese Journal of Applied Physics. 36 (3S): 1569. Bibcode:1997JaJAP..36.1569K. doi:10.1143/JJAP.36.1569. ISSN 1347-4065.
  24. Ahmed, Khaled Z.; Ibok, Effiong E.; Song, Miryeong; Yeap, Geoffrey; Xiang, Qi; Bang, David S.; Lin, Ming-Ren (1998). "Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides". 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216): 160–161. doi:10.1109/VLSIT.1998.689240. ISBN 0-7803-4770-6.
  25. Ahmed, Khaled Z.; Ibok, Effiong E.; Song, Miryeong; Yeap, Geoffrey; Xiang, Qi; Bang, David S.; Lin, Ming-Ren (1998). "Sub-100 nm nMOSFETs with direct tunneling thermal, nitrous and nitric oxides". 56th Annual Device Research Conference Digest (Cat. No.98TH8373): 10–11. doi:10.1109/DRC.1998.731099. ISBN 0-7803-4995-4.
  26. Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). "Extreme scaling with ultra-thin Si channel MOSFETs". Digest. International Electron Devices Meeting: 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2.
  27. Schwierz, Frank; Wong, Hei; Liou, Juin J. (2010). Nanometer CMOS. Pan Stanford Publishing. p. 17. ISBN 9789814241083.
  28. "IBM claims world's smallest silicon transistor - TheINQUIRER". Theinquirer.net. 2002-12-09. Retrieved 7 December 2017.
  29. Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003: 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5.
  30. "1963: Complementary MOS Circuit Configuration is Invented". Computer History Museum. Retrieved 6 July 2019.
  31. Sah, Chih-Tang; Wanlass, Frank (February 1963). "Nanowatt logic using field-effect metal–oxide semiconductor triodes". 1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. VI: 32–33. doi:10.1109/ISSCC.1963.1157450.
  32. Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. p. 330. ISBN 9783540342588.
  33. Aitken, A.; Poulsen, R. G.; MacArthur, A. T. P.; White, J. J. (December 1976). "A fully plasma etched-ion implanted CMOS process". 1976 International Electron Devices Meeting: 209–213. doi:10.1109/IEDM.1976.189021.
  34. "1978: Double-well fast CMOS SRAM (Hitachi)" (PDF). Semiconductor History Museum of Japan. Retrieved 5 July 2019.
  35. Masuhara, Toshiaki; Minato, Osamu; Sasaki, Toshio; Sakai, Yoshio; Kubo, Masaharu; Yasui, Tokumasa (February 1978). "A high-speed, low-power Hi-CMOS 4K static RAM". 1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XXI: 110–111. doi:10.1109/ISSCC.1978.1155749.
  36. Masuhara, Toshiaki; Minato, Osamu; Sakai, Yoshi; Sasaki, Toshio; Kubo, Masaharu; Yasui, Tokumasa (September 1978). "Short Channel Hi-CMOS Device and Circuits". ESSCIRC 78: 4th European Solid State Circuits Conference - Digest of Technical Papers: 131–132.
  37. Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). CORE. Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019.
  38. Chwang, R. J. C.; Choi, M.; Creek, D.; Stern, S.; Pelley, P. H.; Schutz, Joseph D.; Bohr, M. T.; Warkentin, P. A.; Yu, K. (February 1983). "A 70ns high density CMOS DRAM". 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XXVI: 56–57. doi:10.1109/ISSCC.1983.1156456.
  39. Mano, Tsuneo; Yamada, J.; Inoue, Junichi; Nakajima, S. (February 1983). "Submicron VLSI memory circuits". 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XXVI: 234–235. doi:10.1109/ISSCC.1983.1156549.
  40. Hu, G. J.; Taur, Yuan; Dennard, Robert H.; Terman, L. M.; Ting, Chung-Yu (December 1983). "A self-aligned 1-μm CMOS technology for VLSI". 1983 International Electron Devices Meeting: 739–741. doi:10.1109/IEDM.1983.190615.
  41. Sumi, T.; Taniguchi, Tsuneo; Kishimoto, Mikio; Hirano, Hiroshige; Kuriyama, H.; Nishimoto, T.; Oishi, H.; Tetakawa, S. (1987). "A 60ns 4Mb DRAM in a 300mil DIP". 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XXX: 282–283. doi:10.1109/ISSCC.1987.1157106.
  42. Mano, Tsuneo; Yamada, J.; Inoue, Junichi; Nakajima, S.; Matsumura, Toshiro; Minegishi, K.; Miura, K.; Matsuda, T.; Hashimoto, C.; Namatsu, H. (1987). "Circuit technologies for 16Mb DRAMs". 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. XXX: 22–23. doi:10.1109/ISSCC.1987.1157158.
  43. Hanafi, Hussein I.; Dennard, Robert H.; Taur, Yuan; Haddad, Nadim F.; Sun, J. Y. C.; Rodriguez, M. D. (September 1987). "0.5 μm CMOS Device Design and Characterization". ESSDERC '87: 17th European Solid State Device Research Conference: 91–94.
  44. Kasai, Naoki; Endo, Nobuhiro; Kitajima, Hiroshi (December 1987). "0.25 μm CMOS technology using P+polysilicon gate PMOSFET". 1987 International Electron Devices Meeting: 367–370. doi:10.1109/IEDM.1987.191433.
  45. Inoue, M.; Kotani, H.; Yamada, T.; Yamauchi, Hiroyuki; Fujiwara, A.; Matsushima, J.; Akamatsu, Hironori; Fukumoto, M.; Kubota, M.; Nakao, I.; Aoi (1988). "A 16mb Dram with an Open Bit-Line Architecture". 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers: 246–. doi:10.1109/ISSCC.1988.663712.
  46. Shahidi, Ghavam G.; Davari, Bijan; Taur, Yuan; Warnock, James D.; Wordeman, Matthew R.; McFarland, P. A.; Mader, S. R.; Rodriguez, M. D. (December 1990). "Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing". International Technical Digest on Electron Devices: 587–590. doi:10.1109/IEDM.1990.237130.
  47. "Memory". STOL (Semiconductor Technology Online). Retrieved 25 June 2019.
  48. "0.18-micron Technology". TSMC. Retrieved 30 June 2019.
  49. "NEC test-produces world's smallest transistor". Thefreelibrary.com. Retrieved 7 December 2017.
  50. Sekigawa, Toshihiro; Hayashi, Yutaka (August 1984). "Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate". Solid-State Electronics. 27 (8): 827–828. Bibcode:1984SSEle..27..827S. doi:10.1016/0038-1101(84)90036-4. ISSN 0038-1101.
  51. Koike, Hanpei; Nakagawa, Tadashi; Sekigawa, Toshiro; Suzuki, E.; Tsutsumi, Toshiyuki (23 February 2003). "Primary Consideration on Compact Modeling of DG MOSFETs with Four-terminal Operation Mode" (PDF). TechConnect Briefs. 2 (2003): 330–333.
  52. Davari, Bijan; Chang, Wen-Hsing; Wordeman, Matthew R.; Oh, C. S.; Taur, Yuan; Petrillo, Karen E.; Rodriguez, M. D. (December 1988). "A high performance 0.25 mu m CMOS technology". Technical Digest., International Electron Devices Meeting: 56–59. doi:10.1109/IEDM.1988.32749.
  53. Davari, Bijan; Wong, C. Y.; Sun, Jack Yuan-Chen; Taur, Yuan (December 1988). "Doping of n/sup +/ and p/sup +/ polysilicon in a dual-gate CMOS process". Technical Digest., International Electron Devices Meeting: 238–241. doi:10.1109/IEDM.1988.32800.
  54. Masuoka, Fujio; Takato, Hiroshi; Sunouchi, Kazumasa; Okabe, N.; Nitayama, Akihiro; Hieda, K.; Horiguchi, Fumio (December 1988). "High performance CMOS surrounding-gate transistor (SGT) for ultra high density LSIs". Technical Digest., International Electron Devices Meeting: 222–225. doi:10.1109/IEDM.1988.32796.
  55. Brozek, Tomasz (2017). Micro- and Nanoelectronics: Emerging Device Challenges and Solutions. CRC Press. p. 117. ISBN 9781351831345.
  56. Ishikawa, Fumitaro; Buyanova, Irina (2017). Novel Compound Semiconductor Nanowires: Materials, Devices, and Applications. CRC Press. p. 457. ISBN 9781315340722.
  57. Colinge, J.P. (2008). FinFETs and Other Multi-Gate Transistors. Springer Science & Business Media. p. 11. ISBN 9780387717517.
  58. Hisamoto, Digh; Kaga, Toru; Kawamoto, Yoshifumi; Takeda, Eiji (December 1989). "A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET". International Technical Digest on Electron Devices Meeting: 833–836. doi:10.1109/IEDM.1989.74182.
  59. "IEEE Andrew S. Grove Award Recipients". IEEE Andrew S. Grove Award. Institute of Electrical and Electronics Engineers. Retrieved 4 July 2019.
  60. Tsu‐Jae King, Liu (June 11, 2012). "FinFET: History, Fundamentals and Future". University of California, Berkeley. Symposium on VLSI Technology Short Course. Archived from the original on 28 May 2016. Retrieved 9 July 2019.
  61. Hisamoto, Digh; Hu, Chenming; Liu, Tsu-Jae King; Bokor, Jeffrey; Lee, Wen-Chin; Kedzierski, Jakub; Anderson, Erik; Takeuchi, Hideki; Asano, Kazuya (December 1998). "A folded-channel MOSFET for deep-sub-tenth micron era". International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217): 1032–1034. doi:10.1109/IEDM.1998.746531. ISBN 0-7803-4774-9.
  62. Hu, Chenming; Choi, Yang‐Kyu; Lindert, N.; Xuan, P.; Tang, S.; Ha, D.; Anderson, E.; Bokor, J.; Tsu-Jae King, Liu (December 2001). "Sub-20 nm CMOS FinFET technologies". International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224): 19.1.1–19.1.4. doi:10.1109/IEDM.2001.979526. ISBN 0-7803-7050-3.
  63. Ahmed, Shibly; Bell, Scott; Tabery, Cyrus; Bokor, Jeffrey; Kyser, David; Hu, Chenming; Liu, Tsu-Jae King; Yu, Bin; Chang, Leland (December 2002). "FinFET scaling to 10 nm gate length" (PDF). Digest. International Electron Devices Meeting: 251–254. CiteSeerX 10.1.1.136.3757. doi:10.1109/IEDM.2002.1175825. ISBN 0-7803-7462-2.
  64. Lee, Hyunjin; Choi, Yang-Kyu; Yu, Lee-Eun; Ryu, Seong-Wan; Han, Jin-Woo; Jeon, K.; Jang, D.Y.; Kim, Kuk-Hwan; Lee, Ju-Hyun; et al. (June 2006), "Sub-5nm All-Around Gate FinFET for Ultimate Scaling", Symposium on VLSI Technology, 2006: 58–59, doi:10.1109/VLSIT.2006.1705215, hdl:10203/698, ISBN 978-1-4244-0005-8
  65. "Still Room at the Bottom (nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012
  66. Weimer, Paul K. (June 1962). "The TFT A New Thin-Film Transistor". Proceedings of the IRE. 50 (6): 1462–1469. doi:10.1109/JRPROC.1962.288190. ISSN 0096-8390.
  67. Kuo, Yue (1 January 2013). "Thin Film Transistor Technology—Past, Present, and Future" (PDF). The Electrochemical Society Interface. 22 (1): 55–61. doi:10.1149/2.F06131if. ISSN 1064-8208.
  68. Ye, Peide D.; Xuan, Yi; Wu, Yanqing; Xu, Min (2010). "Atomic-Layer Deposited High-k/III-V Metal-Oxide-Semiconductor Devices and Correlated Empirical Model". In Oktyabrsky, Serge; Ye, Peide (eds.). Fundamentals of III-V Semiconductor MOSFETs. Springer Science & Business Media. pp. 173–194. doi:10.1007/978-1-4419-1547-4_7. ISBN 978-1-4419-1547-4.
  69. Brody, T. P.; Kunig, H. E. (October 1966). "A HIGH‐GAIN InAs THIN‐FILM TRANSISTOR". Applied Physics Letters. 9 (7): 259–260. Bibcode:1966ApPhL...9..259B. doi:10.1063/1.1754740. ISSN 0003-6951.
  70. Woodall, Jerry M. (2010). Fundamentals of III-V Semiconductor MOSFETs. Springer Science & Business Media. pp. 2–3. ISBN 9781441915474.
  71. Kahng, Dawon; Sze, Simon Min (July–August 1967). "A floating gate and its application to memory devices". The Bell System Technical Journal. 46 (6): 1288–1295. Bibcode:1967ITED...14Q.629K. doi:10.1002/j.1538-7305.1967.tb01738.x.
  72. Wegener, H. A. R.; Lincoln, A. J.; Pao, H. C.; O'Connell, M. R.; Oleksiak, R. E.; Lawrence, H. (October 1967). "The variable threshold transistor, a new electrically-alterable, non-destructive read-only storage device". 1967 International Electron Devices Meeting. 13: 70. doi:10.1109/IEDM.1967.187833.
  73. Lin, Hung Chang; Iyer, Ramachandra R. (July 1968). "A Monolithic Mos-Bipolar Audio Amplifier". IEEE Transactions on Broadcast and Television Receivers. 14 (2): 80–86. doi:10.1109/TBTR1.1968.4320132.
  74. Alvarez, Antonio R. (1990). "Introduction To BiCMOS". BiCMOS Technology and Applications. Springer Science & Business Media. pp. 1–20 (2). doi:10.1007/978-1-4757-2029-7_1. ISBN 9780792393849.
  75. Lin, Hung Chang; Iyer, Ramachandra R.; Ho, C. T. (October 1968). "Complementary MOS-bipolar structure". 1968 International Electron Devices Meeting: 22–24. doi:10.1109/IEDM.1968.187949.
  76. "Advances in Discrete Semiconductors March On". Power Electronics Technology. Informa: 52–6. September 2005. Archived (PDF) from the original on 22 March 2006. Retrieved 31 July 2019.
  77. Oxner, E. S. (1988). Fet Technology and Application. CRC Press. p. 18. ISBN 9780824780500.
  78. Tarui, Y.; Hayashi, Y.; Sekigawa, Toshihiro (September 1969). "Diffusion Self-Aligned MOST; A New Approach for High Speed Device". Proceedings of the 1st Conference on Solid State Devices. doi:10.7567/SSDM.1969.4-1.
  79. McLintock, G. A.; Thomas, R. E. (December 1972). "Modelling of the double-diffused MOST's with self-aligned gates". 1972 International Electron Devices Meeting: 24–26. doi:10.1109/IEDM.1972.249241.
  80. Bergveld, P. (January 1970). "Development of an Ion-Sensitive Solid-State Device for Neurophysiological Measurements". IEEE Transactions on Biomedical Engineering. BME-17 (1): 70–71. doi:10.1109/TBME.1970.4502688. PMID 5441220.
  81. Chris Toumazou; Pantelis Georgiou (December 2011). "40 years of ISFET technology: From neuronal sensing to DNA sequencing". Electronics Letters. doi:10.1049/el.2011.3231. Retrieved 13 May 2016.
  82. Tarui, Y.; Hayashi, Y.; Sekigawa, Toshihiro (October 1970). "DSA enhancement - Depletion MOS IC". 1970 International Electron Devices Meeting: 110. doi:10.1109/IEDM.1970.188299.
  83. Duncan, Ben (1996). High Performance Audio Power Amplifiers. Elsevier. pp. 177–8, 406. ISBN 9780080508047.
  84. Baliga, B. Jayant (2015). The IGBT Device: Physics, Design and Applications of the Insulated Gate Bipolar Transistor. William Andrew. pp. xxviii, 5–12. ISBN 9781455731534.
  85. Higuchi, H.; Kitsukawa, Goro; Ikeda, Takahide; Nishio, Y.; Sasaki, N.; Ogiue, Katsumi (December 1984). "Performance and structures of scaled-down bipolar devices merged with CMOSFETs". 1984 International Electron Devices Meeting: 694–697. doi:10.1109/IEDM.1984.190818.
  86. Deguchi, K.; Komatsu, Kazuhiko; Miyake, M.; Namatsu, H.; Sekimoto, M.; Hirata, K. (1985). "Step-and-Repeat X-ray/Photo Hybrid Lithography for 0.3 μm Mos Devices". 1985 Symposium on VLSI Technology. Digest of Technical Papers: 74–75.
  87. Momose, H.; Shibata, Hideki; Saitoh, S.; Miyamoto, Jun-ichi; Kanzaki, K.; Kohyama, Susumu (1985). "1.0-/spl mu/m n-Well CMOS/Bipolar Technology". IEEE Journal of Solid-State Circuits. 20 (1): 137–143. Bibcode:1985IJSSC..20..137M. doi:10.1109/JSSC.1985.1052286.
  88. Lee, Han-Sheng; Puzio, L.C. (November 1986). "The electrical properties of subquarter-micrometer gate-length MOSFET's". IEEE Electron Device Letters. 7 (11): 612–614. Bibcode:1986IEDL....7..612H. doi:10.1109/EDL.1986.26492.
  89. Shahidi, Ghavam G.; Antoniadis, Dimitri A.; Smith, Henry I. (December 1986). "Electron velocity overshoot at 300 K and 77 K in silicon MOSFETs with submicron channel lengths". 1986 International Electron Devices Meeting: 824–825. doi:10.1109/IEDM.1986.191325.
  90. Davari, Bijan; Ting, Chung-Yu; Ahn, Kie Y.; Basavaiah, S.; Hu, Chao-Kun; Taur, Yuan; Wordeman, Matthew R.; Aboelfotoh, O. (May 1987). "Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide". 1987 Symposium on VLSI Technology. Digest of Technical Papers: 61–62.
  91. Havemann, Robert H.; Eklund, R. E.; Tran, Hiep V.; Haken, R. A.; Scott, D. B.; Fung, P. K.; Ham, T. E.; Favreau, D. P.; Virkus, R. L. (December 1987). "An 0.8 #181;m 256K BiCMOS SRAM technology". 1987 International Electron Devices Meeting: 841–843. doi:10.1109/IEDM.1987.191564.
  92. Kawaura, Hisao; Sakamoto, Toshitsugu; Baba, Toshio; Ochiai, Yukinori; Fujita, Jun-ichi; Matsui, Shinji; Sone, J. (1997). "Transistor operations in 30-nm-gate-length EJ-MOSFETs". 1997 55th Annual Device Research Conference Digest: 14–15. doi:10.1109/DRC.1997.612456. ISBN 0-7803-3911-8.
  93. Kawaura, Hisao; Sakamoto, Toshitsugu; Baba, Toshio (12 June 2000). "Observation of source-to-drain direct tunneling current in 8 nm gate electrically variable shallow junction metal–oxide–semiconductor field-effect transistors". Applied Physics Letters. 76 (25): 3810–3812. Bibcode:2000ApPhL..76.3810K. doi:10.1063/1.126789. ISSN 0003-6951.
  94. Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. pp. 362–363. ISBN 9783540342588. The i1103 was manufactured on a 6-mask silicon-gate P-MOS process with 8 μm minimum features. The resulting product had a 2,400 μm, 2 memory cell size, a die size just under 10 mm2, and sold for around $21.
  95. http://www.listoid.com/list/142
  96. "Design case history: the Commodore 64" (PDF). IEEE Spectrum. Retrieved 1 September 2019.
  97. Mueller, S (2006-07-21). "Microprocessors from 1971 to the Present". informIT. Retrieved 2012-05-11.
  98. "Amiga Manual: Amiga 3000+ System Specification 1991".
  99. "Archived copy". Archived from the original on 2012-07-10. Retrieved 2012-09-10.CS1 maint: archived copy as title (link)
  100. "EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP" (PDF). Sony. April 21, 2003. Retrieved 26 June 2019.
  101. Krewell, Kevin (21 October 2002). "Fujitsu's SPARC64 V Is Real Deal". Microprocessor Report.
  102. "EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP" (PDF). Sony. April 21, 2003. Retrieved 26 June 2019.
  103. "ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資". pc.watch.impress.co.jp. Archived from the original on 2016-08-13.
  104. TG Daily – AMD preps 65 nm Turion X2 processors Archived 2007-09-13 at the Wayback Machine
  105. http://focus.ti.com/pdfs/wtbu/ti_omap3family.pdf
  106. "Panasonic starts to sell a New-generation UniPhier System LSI". Panasonic. October 10, 2007. Retrieved 2 July 2019.
  107. "Toshiba Makes Major Advances in NAND Flash Memory with 3-bit-per-cell 32nm generation and with 4-bit-per-cell 43nm technology". Toshiba. 11 February 2009. Retrieved 21 June 2019.
  108. "Intel Debuts 32-NM Westmere Desktop Processors". InformationWeek, 7 January 2010. Retrieved 2011-12-17.
  109. Sal Cangeloso (February 4, 2010). "Intel's 6-core 32nm processors arriving soon". Geek.com. Retrieved November 11, 2011.
  110. "Ambarella A7L Enables the Next Generation of Digital Still Cameras with 1080p60 Fluid Motion Video". News release. September 26, 2011. Retrieved November 11, 2011.
  111. Article reporting Hynix 26 nm technology announcement
  112. Toshiba launches 24nm process NAND flash memory
  113. Intel launches Ivy Bridge...
  114. "History". Samsung Electronics. Samsung. Retrieved 19 June 2019.
  115. "16/12nm Technology". TSMC. Retrieved 30 June 2019.
  116. EETimes Intel Rolls 14nm Broadwell in Vegas
  117. "AMD Zen Architecture Overview". Tech4Gizmos. 2015-12-04. Retrieved 2019-05-01.
  118. "Samsung Mass Producing 128Gb 3-bit MLC NAND Flash". Tom's Hardware. 11 April 2013. Retrieved 21 June 2019.
  119. Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology, Oct 2016
  120. "10nm Technology". TSMC. Retrieved 30 June 2019.
  121. http://www.samsung.com/us/explore/galaxy-s8/buy/
  122. techinsights.com. "10nm Rollout Marching Right Along". www.techinsights.com. Archived from the original on 2017-08-03. Retrieved 2017-06-30.
  123. "7nm Technology". TSMC. Retrieved 30 June 2019.
  124. TSMC ramping up 7nm chip production Monica Chen, Hsinchu; Jessie Shen, DIGITIMES Friday 22 June 2018
  125. "Apple's A12 Bionic is the first 7-nanometer smartphone chip". Engadget. Retrieved 2018-09-20.
  126. Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". www.anandtech.com. Retrieved 2019-05-31.
  127. TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology (press release), TSMC, 3 April 2019
  128. "TSMC Plans New Fab for 3nm". EE Times. 12 December 2016. Retrieved 26 September 2019.
  129. Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", www.tomshardware.com
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.