3 nm process

In semiconductor manufacturing, the 3 nm process is the next die shrink after the 5-nanometre MOSFET technology node. As of 2019, Samsung and TSMC have announced plans to put a 3 nm semiconductor node into commercial production. It is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology.

History

Research and technology demos

In 1985, a Nippon Telegraph and Telephone (NTT) research team fabricated a MOSFET (NMOS) device with a channel length of 150 nm and gate oxide thickness of 2.5 nm.[1] In 1998, an Advanced Micro Devices (AMD) research team fabricated a MOSFET (NMOS) device with a channel length of 50 nm and oxide thickness of 1.3 nm.[2][3]

In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes.[4][5] In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology.[6][7]

Commercialization history

In late 2016, TSMC announced plans to construct a 5 nm–3 nm node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.[8]

In 2017, TSMC announced it was to begin construction of the 3 nm semiconductor fabrication plant at the Tainan Science Park in Taiwan.[9] TSMC plans to start volume production of the 3 nm process node in 2023.[10][11][12][13][14]

In early 2018, IMEC and Cadence stated they had taped out 3 nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.[15]

In early 2019, Samsung presented plans to manufacture 3 nm GAAFET (gate-all-around field-effect transistors) at the 3 nm node in 2021;[16][17] Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm 'nodes'.[18][19]

In December 2019, Intel announced plans for 3 nm production in 2025.[20]

In January 2020, Samsung announced the production of the world's first 3 nm GAAFET process prototype, and said that it is targeting mass production in 2021.[21]

Beyond 3 nm

The ITRS uses (as of 2017) the terms "2.1 nm", "1.5 nm", and "1.0 nm" as generic terms for the nodes after 3 nm.[22][23] "2-nanometre" (2 nm) and "14 angstrom" (14 Å or 1.4 nm) nodes have also been (in 2017) tentatively identified by An Steegen (of IMEC) as future production nodes after 3 nm, with hypothesized introduction dates of around 2024, and beyond 2025 respectively.[24]

In late 2018, TSMC chairman Mark Liu predicted chip scaling would continue to 3 nm and 2 nm nodes;[25] however, as of 2019 other semiconductor specialists were undecided as to whether nodes beyond 3 nm could become viable.[26] TSMC began research on 2nm in 2019.[27]

In December 2019, Intel announced plans for 1.4 nm production in 2029.[20]

References

Kobayashi, Toshio; Horiguchi, Seiji; Miyake, M.; Oda, M.; Kiuchi, K. (December 1985). "Extremely high transconductance (above 500 mS/mm) MOSFET with 2.5 nm gate oxide". 1985 International Electron Devices Meeting: 761–763. doi:10.1109/IEDM.1985.191088. S2CID 22309664.
Ahmed, Khaled Z.; Ibok, Effiong E.; Song, Miryeong; Yeap, Geoffrey; Xiang, Qi; Bang, David S.; Lin, Ming-Ren (1998). "Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides". 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216): 160–161. doi:10.1109/VLSIT.1998.689240. ISBN 0-7803-4770-6. S2CID 109823217.
Ahmed, Khaled Z.; Ibok, Effiong E.; Song, Miryeong; Yeap, Geoffrey; Xiang, Qi; Bang, David S.; Lin, Ming-Ren (1998). "Sub-100 nm nMOSFETs with direct tunneling thermal, nitrous and nitric oxides". 56th Annual Device Research Conference Digest (Cat. No.98TH8373): 10–11. doi:10.1109/DRC.1998.731099. ISBN 0-7803-4995-4. S2CID 1849364.
Schwierz, Frank; Wong, Hei; Liou, Juin J. (2010). Nanometer CMOS. Pan Stanford Publishing. p. 17. ISBN 9789814241083.
Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003: 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267.
"Still Room at the Bottom (nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012
Lee, Hyunjin; Choi, Yang-Kyu; Yu, Lee-Eun; Ryu, Seong-Wan; Han, Jin-Woo; Jeon, K.; Jang, D.Y.; Kim, Kuk-Hwan; Lee, Ju-Hyun; et al. (June 2006), "Sub-5nm All-Around Gate FinFET for Ultimate Scaling", Symposium on VLSI Technology, 2006: 58–59, doi:10.1109/VLSIT.2006.1705215, hdl:10203/698, ISBN 978-1-4244-0005-8
Patterson, Alan (12 December 2016), "TSMC Plans New Fab for 3nm", www.eetimes.com
Patterson, Alan (2 October 2017), "TSMC Aims to Build World's First 3-nm Fab", www.eetimes.com
Zafar, Ramish (15 May 2019), TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report
"TSMC to start production on 5nm in second half of 2020, 3nm in 2022". www.techspot.com.
Armasu 2019-12-06T20:26:59Z, Lucian. "Report: TSMC To Start 3nm Volume Production In 2022". Tom's Hardware.
"TSMC 3nm process fab starts construction - mass production in 2023". Gizchina.com. 25 October 2019.
Friedman, Alan. "TSMC starts constructing facilities to turn out 3nm chips by 2023". Phone Arena.
"Imec and Cadence Tape Out Industry's First 3nm Test Chip", www.cadence.com (press release), 28 February 2018
Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", www.tomshardware.com
Samsung: 3nm process is one year ahead of TSMC in GAA and three years ahead of Intel, 6 August 2019
Armasu, Lucian (25 May 2017), "Samsung Reveals 4nm Process Generation, Full Foundry Roadmap", www.tomshardware.com
Cutress, Ian. "Samsung Announces 3nm GAA MBCFET PDK, Version 0.1". www.anandtech.com.
Cutress, Dr Ian. "Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm". www.anandtech.com.
Broekhuijsen 2020-01-03T16:28:57Z, Niels. "Samsung Prototypes First Ever 3nm GAAFET Semiconductor". Tom's Hardware. Retrieved 10 February 2020.
INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - EXECUTIVE SUMMARY (PDF), ITRS, 2017, Table ES2, p.18
INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017, archived from the original (PDF) on 25 October 2018, retrieved 18 April 2019
Merritt, Rick (19 May 2017), "4 Views of the Silicon Roadmap - Distant hope for a 14-angstrom node", www.eetimes.com
Patterson, Alan (12 September 2018), "TSMC: Chip Scaling Could Accelerate", www.eetimes.com
Merritt, Rick (4 March 2019), "SPIE Conference Predicts Bumpy Chip Roadmap", www.eetasia.com
Zafar, Ramish (12 June 2019). "TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report".

Semiconductor device fabrication

MOSFET scaling (process nodes)
010 µm – 1971 006 µm – 1974 003 µm – 1977 1.5 µm – 1981 001 µm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018
Future 005 nm – ~2020 003 nm – ~2022
Half-nodes Density CMOS Device (multi-gate) Moore's law Semiconductor Nanoelectronics