Multi-level cell

Flash memory stores data in individual memory cells, which are made of floating-gate MOSFET transistors. Traditionally, each cell had two possible states (each with one voltage level), so one bit of data was stored in each cell in so-called single-level cells, or SLC flash memory. SLC memory has the advantage of higher write speeds, lower power consumption and higher cell endurance. However, because SLC memory stores less data per cell than MLC memory, it costs more per megabyte of storage to manufacture. Due to higher transfer speeds and expected longer life, SLC flash technology is used in high-performance memory cards. In February 2016, a study was published that showed little difference in practice between the reliability of SLC and MLC.[3]

A single-level cell (SLC) Flash memory may have a lifetime of about 50,000 to 100,000 program/erase cycles.[4]

The primary benefit of MLC flash memory is its lower cost per unit of storage due to the higher data density, and memory-reading software can compensate for a larger bit error rate.[5] The higher error rate necessitates an error correcting code (ECC) that can correct multiple bit errors; for example, the SandForce SF-2500 Flash Controller can correct up to 55 bits per 512-byte sector with an unrecoverable read error rate of less than one sector per 10¹⁷ bits read.[6] The most commonly used algorithm is Bose-Chaudhuri-Hocquenghem (BCH code).[7] Other drawbacks of MLC NAND are lower write speeds, lower number of program-erase cycles and higher power consumption compared to SLC flash memory.

Read speeds can also be lower for MLC NAND than SLC due to the need to read the same data at a second threshold voltage to help resolve errors. TLC and QLC devices may need to read the same data up to 4 and 8 times respectively to obtain values that are correctable by ECC.[8]

MLC flash may have a lifetime of about 1,000 to 10,000 program/erase cycles. This typically necessitates the use of a flash file system which is designed around the limitations of flash memory, such as using wear leveling to extend the useful lifetime of the flash device.

The Intel 8087 used two-bits-per-cell technology, and in 1980 was one of the first devices on the market to use multi-level ROM cells.[9][10] Intel later demonstrated 2-bit multi-level cell (MLC) NOR flash in 1997.[11] NEC demonstrated quad-level cells in 1996, with a 64 Mb flash memory chip storing 2-bit per cell. In 1997, NEC demonstrated a dynamic random-access memory (DRAM) chip with quad-level cells, holding a capacity of 4 Gb. STMicroelectronics also demonstrated quad-level cells in 2000, with a 64 Mb NOR flash memory chip.[12]

As of 2013, some solid-state drives use part of an MLC NAND die as if it were single-bit SLC NAND, giving higher write speeds.[13][14][15]

As of 2018, nearly all commercial MLCs are planar-based (i.e. cells are built on silicon surface) and so subject to scaling limitations. To address this potential problem, the industry is already looking at technologies that can guarantee storage density increases beyond today’s limitations. One of the most promising is 3D Flash, where cells are stacked vertically, thereby avoiding the limitations of planar scaling.[16]

In the past, a few memory devices went the other direction and used two cells per bit to give even lower bit error rates.[17]

Enterprise MLC (eMLC) is a more expensive variant of MLC that is optimized for commercial use. It claims to last longer and be more reliable than normal MLCs while providing cost savings over traditional SLC drives. Although many SSD manufacturers have produced MLC drives slated for enterprise use, only Micron sells raw NAND Flash chips under this designation.[18]

A Triple Level Cell (TLC) is a type of NAND flash memory that stores three bits of information per cell. Toshiba introduced memory with triple-level cells in 2009.[19]

Samsung announced a type of NAND flash that stores three bits of information per cell, with eight total voltage states, coining the term "Triple Level Cell" ("TLC"). Samsung Electronics began mass-producing it in 2010,[20] and it was first seen in Samsung's 840 Series SSDs.[21] Samsung refers to this technology as 3-bit MLC. The negative aspects of MLC are amplified with TLC, but TLC benefits from still higher storage density and lower cost.[22]

In 2013, Samsung introduced V-NAND (Vertical NAND, also known as 3D NAND) with triple-level cells, which had a memory capacity of 128 Gb.[23] They expanded their TLC V-NAND technology to 256 Gb memory in 2015,[20] and 512 Gb in 2017.[24]

Memory that stores four bits per cell are commonly referred to as Quad Level Cell (QLC), following the convention set by TLC. Prior to its invention, QLC referred to cells that can have sixteen voltage states, i.e. ones that store four bits per cell.

In 2009, Toshiba and SanDisk introduced NAND flash memory chips with quad-level cells, storing 4-bit per cell and holding a capacity of 64 Gb.[19][25]

SanDisk X4 flash memory cards, introduced in 2009, was one of the first products based on NAND-memory that stores four bits per cell, commonly referred to as Quad Level Cell (QLC), using 16 discrete charge levels (states) in each individual transistor. The QLC chips used in these memory cards were manufactured by Toshiba, SanDisk and SK Hynix.[26][27]

In 2017, Toshiba introduced V-NAND memory chips with quad-level cells, which have a storage capacity of up to 768 Gb.[28] In 2018, ADATA, Intel, Micron and Samsung have launched some SSD products using QLC NAND memory.[29][30][31][32]

• Flash memory
• Solid-state drive
• StrataFlash

• What is NAND Flash
• NAND Flash Applications
• Linux Memory Technology Devices - NAND
• https://web.archive.org/web/20070927204538/http://www.st.com/stonline/products/literature/anp/12672.htm
• Open NAND Flash Interface