Media-independent interface

MII connector on a Sun Ultra 1 Creator workstation

The media-independent interface (MII) was originally defined as a standard interface to connect a Fast Ethernet (i.e., 100 Mbit/s) media access control (MAC) block to a PHY chip. The MII is standardized by IEEE 802.3u and connects different types of PHYs to MACs. Being media independent means that different types of PHY devices for connecting to different media (i.e. twisted pair, fiber optic, etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission media.

The MII can be used to connect a MAC to an external PHY using a pluggable connector, or directly to a PHY chip which is on the same PCB. On a PC the CNR connector Type B carries MII bus interface signals.

The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.

The original MII transfers network data using 4-bit nibbles in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve 100 Mbit/s throughput. The original MII design has been extended to support reduced signals and increased speeds. Current variants include, reduced media-independent interface (RMII), gigabit media-independent interface (GMII), reduced gigabit media-independent interface (RGMII), 10-gigabit media-independent interface (XGMII) and serial gigabit media-independent interface (SGMII).

Standard MII

The standard MII features a small set of registers:[1]

  • Basic Mode Configuration (#0)
  • Status Word (#1)
  • PHY Identification (#2, #3)
  • Ability Advertisement (#4)
  • Link Partner Ability (#5)
  • Auto Negotiation Expansion (#6)

The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a bitmask with the following meaning:

0x8000 Capable of 100baseT4
0x7800 Capable of 10/100 HD/FD (most common)
0x0040 Preamble suppression permitted
0x0020 Autonegotiation complete
0x0010 Remote fault
0x0008 Capable of Autonegotiation
0x0004 Link established
0x0002 Jabber detected
0x0001 Extended MII register exist.

A more detailed reference on registers exported by MII-compatible PHY's can be found looking at the Linux MII interface definition include/linux/mii.h

Transmitter signals

Signal name Description Direction
TX_CLK Transmit clock PHY to MAC
TXD0 Transmit data bit 0 (transmitted first) MAC to PHY
TXD1 Transmit data bit 1 MAC to PHY
TXD2 Transmit data bit 2 MAC to PHY
TXD3 Transmit data bit 3 MAC to PHY
TX_EN Transmit enable MAC to PHY
TX_ER Transmit error (optional) MAC to PHY

The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for 100 Mbit/s, 2.5 MHz for 10 Mbit/s). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle.

Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY.

More recently, raising transmit error outside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an EEE-capable PHY to enter low power mode.

Receiver signals

Signal name Description Direction
RX_CLK Receive clock PHY to MAC
RXD0 Receive data bit 0 (received first) PHY to MAC
RXD1 Receive data bit 1 PHY to MAC
RXD2 Receive data bit 2 PHY to MAC
RXD3 Receive data bit 3 PHY to MAC
RX_DV Receive data valid PHY to MAC
RX_ER Receive error PHY to MAC
CRS Carrier sense PHY to MAC
COL Collision detect PHY to MAC

The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute.

The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost.

Similar to transmit, raising RX_ER outside a frame is used for special signalling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a "false carrier" indication.

The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists.

In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY.

Management signals

Signal name Description Direction
MDIO Management data Bidirectional
MDC Management data clock MAC to PHY

MDC and MDIO can be shared among multiple PHYs.

Limitations

The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals. For this reason, the reduced media independent interface was developed.

Reduced media-independent interface

Reduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. Four things were changed compared to the MII standard to achieve this:

  • The two clocks TXCLK and RXCLK are replaced by a single clock. This clock is an input to the PHY rather than an output, which allows the clock signal to be shared among all PHYs in a multiport device, such as a switch.
  • The clock frequency is doubled from 25 MHz to 50 MHz, while the data paths are narrowed to 2 bits rather than 4 bits.
  • RXDV and CRS signals are multiplexed to one signal.
  • The COL signal is removed.

These changes mean that RMII uses about half the number of signals compared to MII. The high pin count of MII is more of a burden on microcontrollers with built-in MAC, FPGAs, multiport switches or repeaters, and PC motherboard chipsets than it is for a separate single-port Ethernet MAC, which partially explains why the older MII standard was more wasteful of pins.

RMII signals
Signal name Description Direction
REF_CLK Continuous 50 MHz reference clock Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY
TXD0 Transmit data bit 0 (transmitted first) MAC to PHY
TXD1 Transmit data bit 1 MAC to PHY
TX_EN When high, clock data on TXD0 and TXD1 to the transmitter MAC to PHY
RXD0 Receive data bit 0 (received first) PHY to MAC
RXD1 Receive data bit 1 PHY to MAC
CRS_DV Carrier Sense (CRS) and RX_Data Valid (RX_DV) multiplexed on alternate clock cycles. In 10 Mbit/s mode, it alternates every 10 clock cycles. PHY to MAC
RX_ER Receive error (optional on switches) PHY to MAC
MDIO Management data Bidirectional
MDC Management data clock. MAC to PHY

MDC and MDIO can be shared among multiple PHYs.

The receiver signals are referenced to the REF_CLK, same as the transmitter signals.

This interface requires 9 signals, versus MII's 18. Of those 9, on multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port.

RMII requires a 50 MHz clock where MII requires a 25 MHz clock and data is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI (10 Mbit/s only). Data is sampled on the rising edge only (i.e. it is not double-pumped).

The REF_CLK operates at 50 MHz in both 100 Mbit/s mode and 10 Mbit/s mode. Instead, the transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in 10 Mbit/s mode. The receiver (PHY or MAC) samples the input signals only every ten cycles in 10 Mbit/s mode.

Limitations

There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or 100 Mbit/s mode, so this must also be handled using the MDIO/MDC interface, just like the duplex setting. Version 1.2 of the RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex. Future versions of the RMII standard might specify a way to transmit data over TXD0/TXD1/RXD0/RXD1 pins while TX_EN and CRS_DV are de-asserted. This may allow for real-time conveyance of parameters such as link speed or duplex without needing to poll the MDIO/MDC serial link.

The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC. The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII only for Rx frames. This has the consequence that on RMII the two error conditions "no carrier" and "lost carrier" cannot be detected, and it is difficult or impossible to support shared media such as 10BASE2 or 10BASE5.

Signal levels

TTL signal levels are used for 5 V or 3.3 V logic. Input high threshold is 2.0 V and low is 0.8 V. The specification states that inputs should be 5 V tolerant, however, some popular chips with RMII interfaces are not 5 V tolerant. Given trends in the semiconductor industry and the fact that both ICs are usually on the same board, lack of 5 V tolerance is probably very common, and chips that actually drive 5 V are probably even rarer. 5 V tolerance is probably found primarily on older MII only devices. On the other hand, newer devices may support 2.5 V and 1.8 V logic. FPGAs sufficient to implement MAC are usually not 5 V tolerant.

The RMII signals are treated as lumped signals rather than transmission lines; no termination or controlled impedance is necessary; output drive (and thus slew rates) need to be as slow as possible (rise times from 1–5 ns) to permit this. Drivers should be able to drive 25 pF of capacitance which allows for PCB traces up to 0.30 m. At least the standard says the signals need not be treated as transmission lines. However, at 1 ns edge rates a trace longer than about 2.7 cm , transmission line effects could be a significant problem; at 5 ns, traces can be 5 times longer. The IEEE version of the related MII standard specifies 68 Ω trace impedance.[2] National recommends running 50 Ω traces with 33 Ω (adds to driver output impedance) series termination resistors for either MII or RMII mode to reduce reflections. National also suggests that traces be kept under 0.15 m long and matched within 0.05 m on length to minimize skew.[3]

Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode [4]

Gigabit media-independent interface

Gigabit media-independent Interface (GMII) is an interface between the Media Access Control (MAC) device and the physical layer (PHY). The interface defines speeds up to 1000 Mbit/s, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the media-independent interface (MII) specification. It can also operate on fall-back speeds of 10 or 100 Mbit/s as per the MII specification.

Data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol specific data and a cyclic redundancy check (CRC).

The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as Clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards.[5]

Transmitter signals

Signal name Description
GTXCLK Clock signal for gigabit TX signals (125 MHz)
TXCLK Clock signal for 10/100 Mbit/s signals
TXD[7..0] Data to be transmitted
TXEN Transmitter enable
TXER Transmitter error (used to corrupt a packet)

There are two clocks, depending on whether the PHY is operating at gigabit or 10/100 Mbit/s speeds. For gigabit speeds, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. Otherwise for 10 or 100 Mbit/s the TXCLK (supplied by PHY) is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. The receiver clock is much simpler, with only one clock, which is recovered from the incoming data. Hence the GTXCLK and RXCLK are not coherent.

Receiver signals

Signal name Description
RXCLK Received clock signal (recovered from incoming received data)
RXD[7..0] Received data
RXDV Signifies data received is valid
RXER Signifies data received has errors
COL Collision detect (half-duplex connections only)
CS Carrier sense (half-duplex connections only)

Management signals

Signal name Description
MDC Management interface clock
MDIO Management interface I/O bidirectional pin.

The management interface controls the behavior of the PHY. There are 32 addresses, each containing 16 bits. The first 16 addresses have a defined usage,[6] while the others are device specific. These registers can be used to configure the device (say "only gigabit, full duplex", or "only full duplex") or can be used to determine the current operating mode.

Reduced gigabit media-independent interface

Supported Ethernet speeds
[Mbit/s][MHz]Bits/clock cycle
10 2.5 4
100 25  4
1000 125  8

Reduced gigabit media-independent interface (RGMII) specifies a particular interface between an Ethernet MAC and PHY.

RGMII uses half the number of data pins as used in the GMII interface. This reduction is achieved by clocking data on both the rising and falling edges of the clock in 1000 Mbit/s operation, and by eliminating non-essential signals (carrier-sense and collision-indication). Thus RGMII consists only of: RX_CTL, RXC, RXD[3:0], TX_CTL, TXC, TXD[3:0] (12 pins, as opposed to GMII's 24).

Unlike GMII, the transmit clock signal is always provided by the MAC on the TXC line, rather than being provided by the PHY for 10/100 Mbit/s operation and by the MAC at 1000 Mbit/s. Source-synchronous clocking is used: the clock signal that is output (by either the PHY or the MAC) is synchronous with the data signals. This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink. RGMII v2.0 specifies an optional internal delay, obviating the need for the PCB designer to add delay; this is known as RGMII-ID.

To achieve these data-rates, data is clocked on rising and falling edges for 1000 Mbit/s, and on rising edges only for 10/100 Mbit/s.[7] The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on rising edge and (TXEN xor TXER) on the falling edge. This is the case for both 1000 Mbit/s and 10/100 Mbit/s.[8]

RGMII signals
Signal name Description Direction
TXC Clock signal MAC to PHY
TXD[3..0] Data to be transmitted MAC to PHY
TX_CTL Multiplexing of transmitter enable and transmitter error MAC to PHY
RXC Received clock signal (recovered from incoming received data) PHY to MAC
RXD[3..0] Received data PHY to MAC
RX_CTL Multiplexing of data received is valid and receiver error PHY to MAC
MDC Management interface clock MAC to PHY
MDIO Management interface I/O Bidirectional

RGMII version 1.3[9] uses 2.5V CMOS,[10] whereas RGMII version 2 uses 1.5V HSTL.[11]

Serial gigabit media-independent interface

The serial gigabit media-independent interface (SGMII) is a variant of MII, a standard interface used to connect an Ethernet MAC block to a PHY. It is used for Gigabit Ethernet but can also carry 10/100 Mbit/s Ethernet.

It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs from GMII by its low-power and low pin-count serial 8b/10b-coded interface (commonly referred to as a SerDes). Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input (clock recovery may be used alternatively). 10/100 Mbit/s Ethernet is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz.

Quad serial gigabit media-independent interface

The quad serial gigabit media-independent interface (QSGMII) is a method of combining four SGMII lines into a 5 Gbit/s interface. QSGMII, like SGMII, uses low-voltage differential signaling (LVDS) for the TX and RX data, and a single LVDS clock signal.

QSGMII uses significantly fewer signal lines than four SGMII busses.

10 gigabit media-independent interface

10 gigabit media-independent interface (XGMII) is a standard defined in IEEE 802.3 for connecting full duplex 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board. It is composed from two 32-bit datapaths (Rx & Tx) and two four-bit control flows (Rxc and Txc), operating at 156.25 MHz DDR (312.5 MT/s).

Typically used for on-chip connections; in chip-to-chip usage mostly replaced by XAUI.

See also

References

  1. ↑ IEEE Standard 802.3: CSMA/CD Access Method and Physical Layer Specifications, Section Two, Chapter 22.2.4 (retrieved on 15-10-2010)
  2. ↑ AN-1469 datasheet
  3. ↑ AN-1469 datasheet p. 5
  4. ↑ AN-1405 schematic.
  5. ↑ "IEEE Standard for Ethernet - Section 3". ieeexplore.ieee.org. IEEE 802.3. 2015. Retrieved 20 April 2018.
  6. ↑ IEEE 802.3,2000–22.2.4 Management Functions
  7. ↑ "Reduced Gigabit Media Independent Interface (RGMII) Version 2.0" (PDF). 2002-04-01. Archived from the original on 2016-03-03.
  8. ↑ "XWAY PHY11G" (PDF).
  9. ↑ "Reduced Gigabit Media Independent Interface (RGMII) Version 1.3" (PDF). 2000-12-10. Archived from the original on 2016-03-03.
  10. ↑ "2.5 V ± 0.2 V (Normal Range) and 1.8 V – 2.7 V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits, JESD8-5A.01" (PDF). 2006-06-01.
  11. ↑ "High Speed Transceiver Logic (HSTL). A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits, JESD8-6" (PDF). 1995-08-01.
  • Texas Instruments – AN-1405 DP83848 RMII
  • Texas Instruments – DP83848C PHY Data Sheet
  • hp.com – RGMIIv2_0_final_hp.pdf RGMII 2002-04-01 Version 2.0
  • Serial-GMII Specification Revision 1.7 (ENG-46158) (PDF), archived from the original (PDF) on 2015-07-14
  • CEVA implementation documentation
  • Altera 10Gb Ethernet IP with XGMII and XAUI interfaces
  • GMII Timing and Electrical Specification
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