Tiger Lake (microarchitecture)

Tiger Lake is an Intel CPU microarchitecture based on the third-generation 10 nm process node (named "10nm++").[1] It will replace Ice Lake,[2] representing the Optimization step in Intel's Process-Architecture-Optimization model.

Tiger Lake
Architecture and classification
Architecturex86-64
Instructionsx86-64, Intel 64
Extensions
Physical specifications
Transistors
  • 10 nm transistors
History
PredecessorIce Lake (Architecture)
SuccessorAlder Lake

Tiger Lake is slated to include quad-core 9 W TDP and 25 W TDP models.[3] It will power some 2020 "Project Athena" laptops.[4] The quad-core 96 EU die measures 13.6 by 10.7 mm (146.1 mm2), which is 19.2% wider than the 11.4 by 10.7 mm (122.5 mm2) quad-core 64 EU Ice Lake die.[5]

Features

  • Intel Willow Cove CPU cores
  • Intel Xe ("Gen12") GPU with up to 96 execution units[6] with some processors using Intel's discrete GPU, DG1[7]
  • HEVC 12-bit, 4:2:2 & 4:4:4 fixed-function hardware decoding & VP9 12-bit & 4:4:4 fixed-function hardware decoding[8]
  • PCI Express 4.0[9]
  • Thunderbolt 4[7]
  • USB4[10]
  • LPDDR5 memory [11]
  • New Deep Learning Boost (DL Boost) extensions for built-in AI training acceleration in Xeon processors[12]
  • A new AVX-512 instruction: Vector Pair Intersection to a Pair of Mask Registers (VP2INTERSECT).[13]
  • Miniaturization of CPU and motherboard into an M.2 SSD-sized small circuit board[7]

See also

  • Process-Architecture-Optimization model

References

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