555 timer IC

It has been falsely hypothesized that the 555 got its name from the three 5 kΩ resistors within the bipolar IC.[9] Hans Camenzind has stated that the part number was arbitrary, thus it was simply a coincidence they matched.[5][8] The "NE" and "SE" prefix letters of the original Signetic parts numbers, NE555 and SE555, were temperature designations for analog chips, where "NE" was commercial temperature family and "SE" was military temperature family.

The internal block diagram and schematic of the 555 timer are highlighted with the same color across all three drawings to clarify how the chip is implemented:[2]

• Green: Between the positive supply voltage V_CC and the ground GND is a voltage divider consisting of three identical resistors, which create two reference voltages at ​¹⁄₃ V_CC and ​²⁄₃ V_CC. The latter is connected to the "Control Voltage" pin. All three resistors have the same resistance, 5 kΩ for bipolar timers, 100 kΩ (or higher) for CMOS timers. It is a false myth that the 555 IC got its name from these three 5 kΩ resistors.[5]
• Yellow: The comparator negative input is connected to the higher-reference voltage divider of ​²⁄₃ V_CC (and "Control" pin), and comparator positive input is connected to the "Threshold" pin.
• Red: The comparator positive input is connected to the lower reference voltage divider of ​¹⁄₃ V_CC, and comparator negative input is connected to the "Trigger" pin.
• Purple: An SR flip-flop stores the state of the timer and is controlled by the two comparators. The "Reset" pin overrides the other two inputs, thus the flip-flop (and therefore the entire timer) can be reset at any time.
• Pink: The output of the flip-flop is followed by an output stage with push-pull (P.P.) output drivers that can load the "Output" pin with up to 200 mA for bipolar timers, lower for CMOS timers.
• Cyan: Also, the output of the flip-flop turns on a transistor that connects the "Discharge" pin to the ground.

• 
  555 internal block diagram[1]
• 
  555 internal schematic of bipolar version
• 
  555 internal schematic of CMOS version

The pinout of the 8-pin 555 timer[1] and 14-pin 556 dual timer[16] are shown in the following table. The 556 is conceptually two 555 timers that share power pins, thus each half is split across two columns.[2]

• 
  Pinout of 555 single timer.[1][2]
• 
  Pinout of 556 dual timer.[16][2]

Schematic of a 555 timer in astable mode.

Waveform in astable mode

In the astable configuration, the 555 timer puts out a continuous stream of rectangular pulses having a specific frequency. The astable configuration is implemented using two resistors, ${\displaystyle R_{1}}$ and ${\displaystyle R_{2}}$, and one capacitor ${\displaystyle C}$. In this configuration, the control pin is not used, thus it is connected to ground through a 10 nF decoupling capacitor to shunt electrical noise. The threshold and trigger pins are connected to the capacitor ${\displaystyle C}$, thus they have the same voltage. Initially, the capacitor ${\displaystyle C}$ is not charged, thus the trigger pin receives zero voltage which is less than a third of the supply voltage. Consequently, the trigger pin causes the output to go high and the internal discharge transistor to go to cut-off mode. Since the discharge pin is no longer short-circuited to ground, the current flows through the two resistors, ${\displaystyle R_{1}}$ and ${\displaystyle R_{2}}$, to the capacitor charging it. The capacitor ${\displaystyle C}$ starts charging until the voltage becomes two-thirds of the supply voltage. At this instance, the threshold pin causes the output to go low and the internal discharge transistor to go into saturation mode. Consequently, the capacitor starts discharging through ${\displaystyle R_{2}}$ till it becomes less than a third of the supply voltage, in which case, the trigger pin causes the output to go high and the internal discharge transistor to go to cut-off mode once again. And the cycle repeats.

In the first pulse, the capacitor charges from zero to two-thirds of the supply voltage, however, in later pulses, it only charges from one-third to two-thirds of the supply voltage. Consequently, the first pulse has a longer high time interval compared to later pulses. Moreover, the capacitor charges through both resistors but only discharges through ${\displaystyle R_{2}}$, thus the high interval is longer than the low interval. This is shown in the following equations.

The high time interval of each pulse is given by:

${\displaystyle t_{high}=\ln(2)\cdot (R_{1}+R_{2})\cdot C}$

The low time interval of each pulse is given by:

${\displaystyle t_{low}=\ln(2)\cdot R_{2}\cdot C}$

Hence, the frequency ${\displaystyle f}$ of the pulse is given by:

${\displaystyle f={\frac {1}{t_{high}+t_{low}}}={\frac {1}{\ln(2)\cdot (R_{1}+2R_{2})\cdot C}}}$[18]

and the duty cycle (%) is given by:

${\displaystyle duty={\frac {t_{high}}{t_{high}+t_{low}}}\cdot 100}$

where ${\displaystyle t}$ is in seconds (time), ${\displaystyle R}$ is in ohms (resistance), ${\displaystyle C}$ is in farads (capacitance), ${\displaystyle \ln(2)}$ is the natural log of 2 constant, which is 0.693147181 (rounded to 9 trailing digits) but commonly is rounded to fewer digits in 555 timer books and datasheets as 0.7 or 0.69 or 0.693.

Resistor ${\displaystyle R_{1}}$ requirements:

• ${\displaystyle W}$ power capability of ${\displaystyle R_{1}}$ must be greater than ${\displaystyle {\frac {V_{cc}\cdot V_{cc}}{R_{1}}}}$, per Ohm's law.

• Particularly with bipolar 555s, low values of ${\displaystyle R_{1}}$ must be avoided so that the output stays saturated near zero volts during discharge, as assumed by the above equation. Otherwise, the output low time will be greater than calculated above.

The first cycle will take appreciably longer than the calculated time, as the capacitor must charge from 0V to ​²⁄₃ of V_CC from power-up, but only from ​¹⁄₃ of V_CC to ​²⁄₃ of V_CC on subsequent cycles.

To have an output high time shorter than the low time (i.e., a duty cycle less than 50%) a fast diode (i.e. 1N4148 signal diode) can be placed in parallel with R₂, with the cathode on the capacitor side. This bypasses R₂ during the high part of the cycle so that the high interval depends only on R₁ and C, with an adjustment based the voltage drop across the diode. The voltage drop across the diode slows charging on the capacitor so that the high time is longer than the expected and often-cited ln(2)*R₁C = 0.693 R₁C. The low time will be the same as above, 0.693 R₂C. With the bypass diode, the high time is

${\displaystyle t_{high}=\ln \left({\frac {2V_{\textrm {cc}}-3V_{\textrm {diode}}}{V_{\textrm {cc}}-3V_{\textrm {diode}}}}\right)\cdot R_{1}\cdot C}$

where V_diode is when the diode's "on" current is ​¹⁄₂ of V_cc/R₁ which can be determined from its datasheet or by testing. As an extreme example, when V_cc= 5 and V_diode= 0.7, high time = 1.00 R₁C which is 45% longer than the "expected" 0.693 R₁C. At the other extreme, when V_cc= 15 and V_diode= 0.3, the high time = 0.725 R₁C which is closer to the expected 0.693 R₁C. The equation reduces to the expected 0.693 R₁C if V_diode= 0.

The operation of RESET in this mode is not well-defined. Some manufacturers' parts will hold the output state to what it was when RESET is taken low, others will send the output either high or low.

Schematic of a 555 in monostable mode. Example values R = 220K, C = 100nF for debouncing a pushbutton.

Waveform in monostable mode

In monostable mode, the output pulse ends when the voltage on the capacitor equals ​²⁄₃ of the supply voltage. The output pulse width can be lengthened or shortened to the need of the specific application by adjusting the values of R and C.[19]

Assume initially the output of the monostable is zero, the output of flip-flop(Q bar) is 1 so that the discharging transistor is on and the voltage across a capacitor is zero. One of the inputs of the upper comparator is at 2/3 of supply voltage and the other is connected to the capacitor. For a lower comparator, one of the inputs is trigger pulse and the other is connected at 1/3 of the supply voltage. Now the capacitor charges towards supply voltage(Vcc). When the trigger input is applied at the trigger pin the output of the lower comparator is 0 and the upper comparator is 0. The output of flip-flop remains unchanged therefore the output is 0. when the voltage across the capacitor crosses the 1/3 of the Vcc the output of lower comparator changes from 0 to 1. Therefore, the output of monostable is one and the discharging transistor is still off and the voltage across capacitor charges towards Vcc from 1/3 of Vcc,

When the voltage across the capacitor crosses 2/3 of VCC, the output of the upper comparator changes from 0 to 1, therefore the output of monostable is 0 and the discharging transistor is on and the capacitor discharges through this transistor as it offers low resistance path. The cycle repeats continuously. The charging and discharging of the capacitor depends on the time constant RC.

The voltage across capacitor is given by vc = Vcc(1-e^(-t/RC)) at t=T. Since vc =(2/3)Vcc, therefore 2/3Vcc = Vcc(1-e^(-T/RC)), thus reduced to T = RC ln(3) seconds.

The output pulse width of time t, which is the time it takes to charge C to ​²⁄₃ of the supply voltage, is given by

${\displaystyle t=\ln(3)\cdot R\cdot C}$

where ${\displaystyle t}$ is in seconds (time), ${\displaystyle R}$ is in ohms (resistance), ${\displaystyle C}$ is in farads (capacitance), ${\displaystyle \ln(3)}$ is the natural log of 3 constant, which is 1.098612289 (rounded to 9 trailing digits) but commonly is rounded to fewer digits in 555 timer books and datasheets as 1.1 or 1.099.

While using the timer IC in monostable mode, the main disadvantage is that the time span between any two triggering pulses must be greater than the RC time constant.[20] Conversely, ignoring closely spaced pulses is done by setting the RC time constant to be larger than the span between spurious triggers. (Example: ignoring switch contact bouncing.)

Schematic of a 555 in bistable flip-flop mode. High-value pull-up resistors should be added to the two inputs.

Inverted SR flip-flop symbol (without /Q) is similar to circuit on right

In bistable mode, the 555 timer acts as an SR flip-flop. The trigger and reset inputs (pins 2 and 4 respectively on a 555) are held high via pull-up resistors while the threshold input (pin 6) is grounded. Thus configured, pulling the trigger momentarily to ground acts as a 'set' and transitions the output pin (pin 3) to V_CC (high state). Pulling the reset input to ground acts as a 'reset' and transitions the output pin to ground (low state). No timing capacitors are required in a bistable configuration. Pin 7 (discharge) is left unconnected, or may be used as an open-collector output.[21]

Schematic of a 555 in bistable schmitt trigger mode. Example values R1 and R2 = 100K, C = 10nF.

Schmitt trigger inverter gate (lower symbol) is similar to circuit on right

A 555 timer can be used to create a Schmitt trigger inverter gate which converts a noisy input into a clean digital output. The input signal should be connected through a series capacitor which then connects to the trigger and threshold pins. A resistor divider, from V_CC to GND, is connected to the previous tied pins. The reset pin is tied to V_CC.

Die of a NE556 dual timer manufactured by STMicroelectronics

Pinout of 556 dual timer.[16][11]

The dual version is called 556. It features two complete 555 timers in a 14 pin package, only the two power supply pins are shared between the two timers.[16][11] In 2020, the bipolar version was available as the NE556,[16], and the CMOS versions were available as the Intersil ICM7556 and Texas Instruments TLC556 and TLC552, see derivatives table in this article.[12][34][33]

Die of a NE558 quad timer manufactured by Signetics

Pinout of 558 quad timer.[2]

558 internal block diagram. It is different than 555 and 556 timers.[2]

The quad version is called 558. It has four reduced-functionality timers in a 16 pin package (four complete 555 timer circuits would have required 26 pins).[2] Since the timers in the 558 is uniquely different than the 555 and 556, the 558 was not as popular. Currently, the 558 is not manufactured by any major chip companies (possibly not by any companies), thus the 558 should be treated as obsolete. Parts are still available from a limited number of sellers as "new old stock" (N.O.S.).[44]

Partial list of differences between 558 and 555 chips:[2]

• One V_CC and one GND, similar to 556 chip.
• Four "Reset" are tied together internally to one external pin (558).
• Four "Control Voltage" are tied together internally to one external pin (558).
• Four "Triggers" are falling-edge sensitive (558), instead of level sensitive (555).
• Two resistors in the voltage divider (558), instead of three resistors (555).
• One comparator (558), instead of two comparators (555).
• Four "Output" are open-collector (O.C.) type (558), instead of push-pull (P.P.) type (555). Since the 558 outputs are open-collector, pull-up resistors are required to "pull up" the output to the positive voltage rail when the output is in a high state. This means the high state only sources a small amount of current through the pull-up resistor.

This circuit requires two 555 or one 556 to generate a variety of sounds.

IBM PC Game Control Adapter[45]
(8-bit ISA card) with 558 quad timer

The Apple II microcomputer used a quad timer 558 in monostable (or "one-shot") mode to interface up to four "game paddles" or two joysticks to the host computer.[46] It also used a single 555 for flashing the display cursor.[47]

The original IBM PC used a similar circuit for the game port on the "Game Control Adapter" 8-bit ISA card (IBM part number 1501300).[45][48] In this joystick interface circuit, the capacitor of the RC network (see Monostable Mode above) was generally a 10 nF capacitor to ground with a series 2.2 KΩ resistor to the game port connector.[45] The external joystick was plugged into the adapter card. Internally it had two potentiometers (100 to 150 KΩ each), one for X and other for Y direction. The center wiper pin of the potentiometer was connected to an Axis wire in the cord and one end of the potentiometer was connected to the 5 Volt wire in the cord. The joystick potentiometer acted as a variable resistor in the RC network.[48] By moving the joystick, the resistance of the joystick increased from a small value up to about 100 kΩ.[48][48]

Software running in the IBM PC computer started the process of determining the joystick position by writing to a special address (ISA bus I/O address 201h).[45][48][49] This would result in a trigger signal to the quad timer, which would cause the capacitor of the RC network to begin charging and cause the quad timer to output a pulse. The width of the pulse was determined by how long it took the capacitor to charge up to ​²⁄₃ of 5 V (or about 3.33 V), which was in turn determined by the joystick position.[48][49] The software then measured the pulse width to determine the joystick position. A wide pulse represented the full-right joystick position, for example, while a narrow pulse represented the full-left joystick position.[48]