List of integrated circuit packaging types

A standard-sized 8-pin dual in-line package (DIP) containing a 555 IC.

Integrated circuits are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of different types of package exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers.

Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture.

Through-hole packages

Through-hole technology uses holes drilled through the PCB for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB.

Three 14-pin (DIP14) plastic dual in-line packages containing IC chips.
AcronymFull nameRemark
SIPSingle in-line package
DIPDual in-line package0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) or 0.6 in (15.24 mm) apart.
CDIPCeramic DIP[1]
CERDIPGlass-sealed ceramic DIP[1]
QIPQuadruple in-line packageLike DIP but with staggered (zig-zag) pins.[1]
SDIPSkinny DIPStandard DIP with 0.1 in (2.54 mm) pin spacing, rows 0.3 in (7.62 mm) apart.[1]
SDIPShrink DIPNon-standard DIP with smaller 0.07 in (1.78 mm) pin spacing.[1]
ZIPZig-zag in-line package
MDIPMolded DIP[2]
PDIPPlastic DIP[1]

Surface mount

AcronymFull nameRemark
CCGACeramic column-grid array (CGA)[3]
CGAColumn-grid array[3]Example
CERPACKCeramic package[4]
CQGP[5]
LLPLead-less lead-frame packageA package with metric pin distribution (0.5–0.8 mm pitch)[6]
LGALand grid array[3]
LTCCLow-temperature co-fired ceramic[7]
MCMMulti-chip module[8]
MICRO SMDXTMicro surface-mount device extended technology[9]Example

Chip carrier

A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing.

AcronymFull nameRemark
BCCBump chip carrier[3]-
CLCCCeramic lead-less chip carrier[1]-
LCCLead-less chip carrier[3]Contacts are recessed vertically.
LCCLeaded chip carrier[3]-
LCCCLeaded ceramic-chip carrier[3]-
DLCCDual lead-less chip carrier (ceramic)[3]-
PLCCPlastic leaded chip carrier[1][3]-

Pin grid arrays

AcronymFull nameRemark
OPGAOrganic pin-grid array-
FCPGAFlip-chip pin-grid array[3]-
PACPin array cartridge[10]-
PGAPin-grid arrayAlso known as PPGA[1]
CPGACeramic pin-grid array[3]-

Flat packages

AcronymFull nameRemark
-Flat-packEarliest version metal/ceramic packaging with flat leads
CFPCeramic flat-pack[3]-
CQFPCeramic quad flat-pack[1][3]Similar to PQFP
BQFPBumpered quad flat-pack[3]-
DFNDual flat-packNo lead[3]
ETQFPExposed thin quad flat-package[11]-
PQFNPower quad flat-packNo-leads, with exposed die-pad[s] for heatsinking[12]
PQFPPlastic quad flat-package[1][3]-
LQFPLow-profile quad flat-package[3]-
QFNQuad flat no-leads packageAlso called as micro lead frame (MLF).[3][13]
QFPQuad flat package[1][3]-
MQFPMetric quad flat-packQFP with metric pin distribution[3]
HVQFNHeat-sink very-thin quad flat-pack, no-leads-
SIDEBRAZE[14][15]
TQFPThin quad flat-pack[1][3]-
VQFPVery-thin quad flat-pack[3]-
TQFNThin quad flat, no-lead-
VQFNVery-thin quad flat, no-lead-
WQFNVery-very-thin quad flat, no-lead-
UQFNUltra-thin quad flat-pack, no-lead-
ODFNOptical dual flat, no-leadIC packaged in transparent packaging used in optical sensor

Small outline packages

AcronymFull nameRemark
SOPSmall-outline package[1]
CSOPCeramic small-outline package
HSOP Thermally-enhanced small-outline package
mini-SOICMini small-outline integrated circuit
MSOPMini small-outline package
PSOPPlastic small-outline package[3]
PSONPlastic small-outline no-lead package
QSOPQuarter-size small-outline packageThe pin spacing are width of 0.635 mm.[3]
SOICSmall-outline integrated circuitAlso known as SOIC NARROW and SOIC WIDE
SOJSmall-outline J-leaded package
SSOPShrink small-outline package[3]
TSOPThin small-outline package[3]Example
TSSOPThin shrink small-outline package[3]
TVSOPThin very-small-outline package[3]
µMAXSimilar to a SOIC. (A Maxim trademark example)
WSONVery-very-thin small-outline no-lead package

Chip-scale packages

Example WL-CSP devices sitting on the face of a U.S. penny. A SOT-23 device is shown for comparison.
AcronymFull nameRemark
CSPChip-scale packagePackage size is no more than 1.2× the size of the silicon chip[16][17]
TCSPTrue chip-size packagePackage is same size as silicon[18]
TDSPTrue die-size packageSame as TCSP[18]
WCSPWafer-level chip-scale package
MICRO SMD-Chip-size package (CSP) developed by National Semiconductor[19]
COBChip-on-boardBare silicon chip, that is usually an integrated circuit, is supplied without a package.
COFChip-on-flexVariation of COB, where a chip is mounted directly to a flex circuit.
COGChip-on-glassVariation of COB, where a chip is mounted directly to a piece of glass - typically an LCD.

Ball grid array

Ball Grid Array BGA uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB.[1][3]

AcronymFull nameRemark
FBGAFine-pitch ball-grid arrayA square or rectangular array of solder balls on one surface[3]
LBGALow-profile ball-grid arrayAlso known as laminate ball-grid array[3]
TEPBGAThermally-enhanced plastic ball-grid array-
CBGACeramic ball-grid array[3]-
OBGAOrganic ball-grid array[3]-
TFBGAThin fine-pitch ball-grid array[3]-
PBGAPlastic ball-grid array[3]-
MAP-BGAMold array process - ball-grid array -
UCSPMicro (μ) chip-scale packageSimilar to a BGA (A Maxim trademark example)[17]
μBGAMicro ball-grid arrayBall spacing less than 1 mm
LFBGALow-profile fine-pitch ball-grid array[3]-
TBGAThin ball-grid array[3]-
SBGASuper ball-grid array[3]Above 500 balls
UFBGAUltra-fine ball-grid array[3]

Transistor, diode, small-pin-count IC packages

A drawing of a ZN414 IC in a TO-18 package
  • MELF: Metal electrode leadless face (usually for resistors and diodes)
  • SOD: Small-outline diode.
  • SOT: Small-outline transistor (also SOT-23, SOT-223, SOT-323).
  • TO-XX: wide range of small pin count packages often used for discrete parts like transistors or diodes.
    • TO-3: Panel-mount with leads
    • TO-5: Metal can package with radial leads
    • TO-18: Metal can package with radial leads
    • TO-39
    • TO-46
    • TO-66: Similar shape to the TO-3 but smaller
    • TO-92: Plastic-encapsulated package with three leads
    • TO-99
    • TO-100
    • TO-126: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
    • TO-220: Through-hole plastic package with a (usually) metal heat sink tab and three leads
    • TO-226[20]
    • TO-247:[21] Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
    • TO-251:[21] Also called IPAK: SMT package similar to the DPAK but with longer leads for SMT or TH mounting
    • TO-252:[21] (also called SOT428, DPAK):[21] SMT package similar to the DPAK but smaller
    • TO-262:[21] Also called I2PAK: SMT package similar to the D2PAK but with longer leads for SMT or TH mounting
    • TO-263:[21] Also called D2PAK: SMT package similar to the TO-220 without the extended tab and mounting hole
    • TO-274:[21] Also called Super-247: SMT package similar to the TO-247 without the mounting hole

Dimension reference

Surface-mount

C
Clearance between IC body and PCB
H
Total Height
T
Lead Thickness
L
Total carrier length
LW
Lead width
LL
Lead length
P
Pitch

Through-hole

C
Clearance between IC body and board
H
Total height
T
Lead thickness
L
Total carrier length
LW
Lead width
LL
Lead length
P
Pitch
WB
IC body width
WL
Lead-to-lead width

Package dimensions

All measurements below are given in mm. To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).

C
Clearance between package body and PCB.
H
Height of package from pin tip to top of package.
T
Thickness of pin.
L
Length of package body only.
LW
Pin width.
LL
Pin length from package to pin tip.
P
Pin pitch (distance between conductors to the PCB).
WB
Width of the package body only.
WL
Length from pin tip to pin tip on the opposite side.

Dual row

ImageFamilyPinNamePackageWBWLHCLPLLTLW
DIP Y Dual inline package 8-DIP6.2–6.487.627.79.2–9.82.54 (0.1 in)3.05–3.61.14–1.73
32-DIP15.242.54 (0.1 in)
LFCSPNLead-frame chip-scale package0.5
MSOP Y Mini small-outline package 8-MSOP34.91.10.1030.650.950.180.17–0.27
10-MSOP34.91.10.1030.50.950.180.17–0.27
16-MSOP34.91.10.104.040.50.950.180.17–0.27
SO
SOIC
SOP		 Y Small-outline integrated circuit 8-SOIC3.95.8–6.21.720.10–0.254.8–5.01.271.050.19–0.250.39–0.46
14-SOIC3.95.8–6.21.720.10–0.258.55–8.751.271.050.19–0.250.39–0.46
16-SOIC3.95.8–6.21.720.10–0.259.9–101.271.050.19–0.250.39–0.46
16-SOIC7.510.00–10.652.650.10–0.3010.1–10.51.271.40.23–0.320.38–0.40
SOTYSmall-outline transistorSOT-23-81.62.81.452.90.950.60.22–0.38
SSOPYShrink small-outline package0.65
TDFNNThin dual flat no-lead8-TDFN330.7–0.830.65N/A0.19–0.3
TSOPYThin small-outline package0.5
TSSOPYThin shrink small-outline package8-TSSOP4.46.41.20.1530.650.09–0.20.19–0.3
µSOPYMicro small-outline package[22]µSOP-84.91.130.65
US8[23]YUS8 package2.33.1.720.5

Quad rows

ImageFamilyPinNamePackageWBWLHCLPLLTLW
PLCCNPlastic leaded chip-carrier1.27
CLCCNCeramic leadless chip-carrier48-CLCC14.2214.222.2114.221.016N/A0.508
LQFPYLow-profile Quad Flat Package0.50
TQFPYThin quad flat-packageTQFP-4410.0012.000.35–0.500.801.000.09–0.200.30–0.45
TQFNNThin quad flat no-lead

LGA

Packagexyz
52-ULGA12 mm17 mm0.65 mm
52-ULGA14 mm18 mm0.10 mm
52-VELGA???

Multi-chip packages

A variety of techniques for interconnecting several chips within a single package have been proposed and researched:

See also

References

  1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 "CPU Collection Museum - Chip Package Information". The CPU Shack. Retrieved 2011-12-15.
  2. ↑ "Archived copy" (PDF). Archived from the original (PDF) on 2011-08-15. Retrieved 2011-02-03.
  3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 "Integrated Circuit, IC Package Types; SOIC. Surface Mount Device Package". Interfacebus.com. Retrieved 2011-12-15.
  4. ↑ "National Semiconductor CERPACK Package Products". National.com. Archived from the original on 2012-02-18. Retrieved 2011-12-15.
  5. ↑ "National Semiconductor CQGP Package Products". National.com. Archived from the original on 2007-10-21. Retrieved 2011-12-15.
  6. ↑ "National's LLP Package". National.com. Archived from the original on 2011-02-13. Retrieved 2011-12-15.
  7. ↑ "LTCC Low Temperature Co-fired Ceramic". Minicaps.com. Retrieved 2011-12-15.
  8. ↑ "IEEE Xplore - Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs". Ieeexplore.ieee.org. doi:10.1109/ASIC.1993.410760. Retrieved 2011-12-15.
  9. ↑ "National Semiconductor Launches New Generation of Ultra-Miniature, High Pin-Count Integrated Circuit Packages". National.com. Retrieved 2011-12-15.
  10. ↑ Meyers, Michael; Jernigan, Scott (2004). Mike Meyers' A+ Guide to PC Hardware. The McGraw-Hill Companies. ISBN 978-0-07-223119-9.
  11. ↑ Archived August 18, 2011, at the Wayback Machine.
  12. ↑ "Press Releases - Motorola Mobility, Inc". Motorola.com. Retrieved 2011-12-15.
  13. ↑ "Xilinx new CPLDs with two I/O banks". Eetasia.com. 2004-12-08. Retrieved 2011-12-15.
  14. ↑ "Packages". Chelseatech.com. 2010-11-15. Retrieved 2011-12-15.
  15. ↑ "Archived copy". Archived from the original on 2008-11-20. Retrieved 2009-10-24.
  16. ↑ "CSP - Chip Scale Package". Siliconfareast.com. Retrieved 2011-12-15.
  17. 1 2 "Understanding Flip-Chip and Chip-Scale Package Technologies and Their Applications - Maxim". Maxim-ic.com. 2007-04-18. Retrieved 2011-12-15.
  18. 1 2 "Chip Scale Review Online". Chipscalereview.com. Retrieved 2011-12-15.
  19. ↑ "Packaging Technology | National Semiconductor – Package Drawings, Part Marking, Package Codes, LLP, micro SMD, Micro-Array". National.com. Archived from the original on 2010-08-01. Retrieved 2011-12-15.
  20. ↑ http://www.siliconfareast.com/to226.htm
  21. 1 2 3 4 5 6 7 http://www.irf.com/package/
  22. ↑ http://pdfserv.maximintegrated.com/package_dwgs/21-0036.PDF
  23. ↑ "Fairchild's TinyLogic family overview" (PDF). March 22, 2013. Archived from the original (PDF) on January 8, 2015.
  24. ↑ Proximity Communication - the Technology, 2004, archived from the original on 2009-07-18
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