Process-Architecture-Optimization model
Process–architecture-optimization is a processor development model adopted in 2016 by Intel. Under this three-phase model, every die shrink is followed by a microarchitecture change and then by an optimizaton. It replaced the two-phase Tick–tock model, adopted by Intel in 2006, because according to Intel the previous model is no longer sustainable.[1][2][3][4]
| Scaling | Process | Architecture | Optimizations |
|---|---|---|---|
| 14 nm | Broadwell | Skylake | Kaby Lake / Amber Lake, Coffee Lake / Whiskey Lake, Cascade Lake |
| 10 nm | Cannon Lake | Ice Lake | Tiger Lake |
References
- ↑ Cutress, Ian. "Intel's 'Tick-Tock' Seemingly Dead, Becomes 'Process-Architecture-Optimization'".
- ↑ eTeknix.com (23 March 2016). "Intel Ditches 'Tick-Tock' for 'Process-Architecture-Optimization' - eTeknix".
- ↑ "Intel Tick-Tock Processor Model Replaced With Process-Architecture-Optimization - Legit Reviews". 23 March 2016.
- ↑ "Intel 7th Gen Core: Process Architecture Optimization". 30 August 2016.
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