MIL-STD-1750A

1750A
Bits 16-bit
Introduced 1980
Design CMOS, GaAs, ECL, SoS
Type RISC
Encoding 16-bit instructions
Extensions FPU, MMU
Registers
General purpose 16 × 16-bit
Floating point Optional in specification

MIL-STD-1750A or 1750A is the formal definition of a 16-bit computer instruction set architecture (ISA), including both required and optional components, as described by the military standard document MIL-STD-1750A (1980).

In addition to the core ISA, the definition defines optional instructions, such as a FPU and MMU. Importantly, the standard does not define the implementation details of a 1750A processor.

Internals

The 1750A supports 216 16-bit words of memory for the core standard. The standard defines an optional memory management unit that allows 220 16-bit words of memory using 512 page mapping registers (in the I/O space), defining separate instruction and data spaces, and keyed memory access control.

Most instructions are 16 bits, although some have a 16-bit extension. The standard computer has 16 general purpose 16-bit registers (0 through 15). Registers 1 through 15 can be used as index registers. Registers 12 through 15 can be used as base registers.

Any of the 16 registers could be used as a stack pointer for the SJS and URS instructions (stack jump subroutine and unstack return subroutine), but only register 15 was used as the stack pointer for the PSHM and POPM instructions (push multiple and pop multiple).

The computer has instructions for 16, and 32-bit binary arithmetic, as well as 32 and 48 bit floating point. I/O is generally via the I/O instructions (XIO and VIO), which have a separate 216 16-bit word address space and may have a specialized bus.

Implementations

Pyramid Semiconductor P1750AE

Because MIL-STD-1750A did not define implementation details, 1750A products are available from a wide variety of companies in the form of component, board, and system-level offerings implemented in myriad technologies, often the most advanced and exotic of their respective periods (e.g. GaAs, ECL, SoS).

Of particular interest is the fact that 1750A systems often offer very high levels of radiation and other hazardous environment protection, making them particularly suited for military, aviation and space applications.

Examples of MIL-STD-1750A implementations include:

  • CPU Technology, Inc. CPU1750A-FB, a high performance 1750A SOC designed to give existing applications a late life performance boost.
  • Dynex Semiconductor MAS281. A radiation hardened SOC implementation on a 64-pin multichip module with an optional MMU.
  • GEC-Plessey RH1750, a radiation-hardened version for aerospace and space flight applications. GEC-Plessey, under its previous incarnation as Marconi Electronic Devices, also initially developed the MAS281 and MA31750A[1] series of processors, later made available through Dynex Semiconductor
  • Honeywell HX1750, fabricated on Honeywell's Silicon on Insulator CMOS (SOI-IV) process giving radiation hardness. The HX1750 includes an FPU and peripherals on chip.
  • Johns Hopkins University Applied Physics Laboratory (JHU/APL) MIL-STD-1750AAV space flight qualified processor. A multi-board silicon on sapphire implementation specifically designed for space flight.
  • Marconi Electronic Devices MIL-STD-1750A.
  • National Semiconductor F9450 series.
  • Pyramid Semiconductor PACE P1750A. The family includes the P1750A CPU, the P1750AE Enhanced CPU, the P1753 Memory Management Unit (MMU), the P1754 Processor Interface Chip (PIC) and the P1757ME Multi-Chip Module. This line was acquired from Performance Semiconductor in 2003.
  • Royal Aircraft Establishment Farnborough MIL-STD-1750A implementation in AMD 2901 bit-slice technology.[2]

Programming

Processors based on MIL-STD-1750A are usually programmed in JOVIAL, a high-level programming language defined by the United States Department of Defense which was derived from ALGOL 58. To a lesser extent, Ada was used.

There are also C compilers, for example Cleanscape XTC-1750A. Older versions of GNU GCC contain support for MIL-STD-1750A; it was declared obsolete in version 3.1, and removed in subsequent versions.

In addition, DDC-I provides its SCORE Integrated Development Environment (IDE) with both Ada95 and C compilers, and TADS (Tartan Ada Development System) Ada83 development environment, both targeting processors based on MIL-STD-1750A.

Deployments

The U.S. Air Force defined the standard in order to have a common computing architecture and thereby reduce the costs of software and computer systems for all military computing needs. This includes embedded tasks such as aircraft and missile control systems as well as more mundane general military computing needs.

The advantages of this concept were recognized outside of the USAF and the 1750A was adopted by numerous other organizations, such as the European Space Agency, NASA, Israeli Aircraft Industries and many projects in academia.

Examples of military aircraft using the 1750A include:

  • IAI Lavi fighter
  • IBM Federal Systems AP-102 Avionics Computer (used in various roles including the USAF F-111 avionics upgrade)
  • US Army AH-64D Apache Longbow Helicopter
  • USAF F-16 Digital Flight Control System and Fire Control Computer
  • USN F-18 RFCS Flight Control Computer

Use in space

Fully space rated implementations make the 1750A one of the few types of computers that are applicable for use in deep space applications. Example spacecraft that use the 1750A are:

References

  1. ↑ "mas31750 DataSheet - PDF - www.BestDatasheets.com". bestdatasheets.com.
  2. ↑ "An Implementation of MIL-STD-1750 Airborne Computer Instruction Set Architecture". dtic.mil.
  3. ↑ "Archived copy" (PDF). Archived from the original (PDF) on 2014-09-01. Retrieved 2014-09-23.
  4. ↑ ftp://ftp.elet.polimi.it/users/Marco.Lovera/ESAGNC08/S08/07_Veeraraghavan.pdf%5Bpermanent+dead+link%5D
  5. ↑ "Orbital ATK" (PDF). orbital.com.
  6. ↑ "Orbital ATK" (PDF). orbital.com.
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