HP 2100

Origins

HP formed Dynac in 1956 to act as a development shop for projects the main company would not normally take on. Their original logo was simply the HP logo turned upside down, forming something approximating "dy". Finding that Westinghouse owned a trademark on the name, in 1958 they changed it to Dymec. The company was brought in-house in 1959 to become the Dymec Division, and in November 1967 was renamed the Palo Alto Division.^[5]

Dymec originally made a variety of products for the HP family, but over time became primarily an integrator, building test equipment and similar systems that were used by HP. In 1964, Kay Magleby and Paul Stoft began experimenting with the use of PDP-5 and PDP-8 computers to act as controllers for their complex test systems. However, they found the machines would require changes to suit their needs. At the time, Digital Equipment Corporation (DEC) was still a small company and a takeover target. However, Dave Packard found Ken Olsen too difficult to deal with.^[5]

Looking for another design they could purchase, Packard was led to the five-person Data Systems, Inc. (DSI) of Detroit. DSI was owned by Union Carbide, and when Packard asked how it was that Union Carbide came to own a computer company, HP Labs manager Barney Oliver replied, "We didn't demand an answer to that question." Bill Hewlett initially refused to consider the development of a "minicomputer", but when Packard reframed it as an "instrument controller" the deal was approved.^[5]

DSI was purchased in 1964 and initially set up at Dymec with four of the original five employees of DSI and a number of other employees coming from HP's instrumentation divisions.^[5][6] The computer group later moved to its own offices in Cupertino in a building purchased from Varian Associates, becoming the Cupertino Division.^[5]

First models

HP 2115A Computer pictured without its power supply.

Led by Magleby, the new division completed the design as the 2116A, which was demonstrated 7–10 November 1966 at the Joint Computer Conference in San Francisco.^[7][8] It was one of the earliest 16-bit minis to hit the market, but is more notable as "an unusual new instrumentation computer" with a highly expandable design and real-time support. The system featured an oversized cabinet that held up to 16 expansion cards, or could be further expanded to 48 cards.

The system launched with 20 different instrumentation cards, including "counters, nuclear scalers, electronic thermometers, digital voltmeters, ac/ohms converters, data amplifiers, and input scanners." An additional set added input/output devices like tape drives, printers, punched cards and paper tape and other peripherals.^[9] Real-time service was provided by having each card slot be assigned a fixed interrupt vector that called the appropriate device driver.^[5]

As the machine entered the market, it quickly became clear it was selling much more rapidly into the business data processing market than the original instrumentation market. This led to the introduction of the 2115A in 1967, which removed much of the expansion capabilities to make a lower-cost offering for the commercial systems market. A further simplified version shipped as the 2114A in 1968,^[5] which had only eight slots, leaving room for the power supply to be incorporated into the main chassis.^[10] The 2115 and 2114 also lacked the extensive DMA control of the 2116, removed some of the mathematical operations, and ran at slightly slower speeds.

HP 2000

In 1969, the company released the 2000A Timeshare System. This was based on the 2116B (a 2116A with an expanded 8k core memory) and a terminal server system that ran HP Time-Shared BASIC. T-S BASIC allowed multiple user accounts to be created^[11] with up to 16 users logged in at once. Depending on the model and hardware configuration, later versions system supported up to 32 simultaneous users.^[12]

The newer models of the 2000, B through F, used newer versions of the underlying CPU as they were introduced. Some models used low-end versions of the same CPU as the terminal server; the 2000F, for instance, used a 2100S as the main CPU and primary storage controller, while a 2100A acted as the terminal server.^[12] The B, C & F models were dual-processor.

In spite of its relatively high costs -the 2000F cost $105,000 in 1974,^[12] or about $521,032 in 2017- it was the first minicomputer to offer time sharing BASIC,^[13] which made it very popular in the early-to-mid 1970s.

2100

HP 2100 computer (upper left), shown with two 7970 tape drives, 7900-series hard disk, 2748 paper tape reader and a 2767A impact printer. The separate front-panel switches and lights were replaced with light-up pushbuttons, which had a tendency to burn out.^[19]

In early 1970, Fred Allard, formerly of Ampex's Memory Core Division, was asked to design a new core memory system for the systems rather than continue purchasing them from Ampex. Using newer 18 mil cores, down from 22 mil, and using a single sense/inhibit line, they were able to fit an 8 kW memory onto a single expansion card. This was used starting in the 2116C models.^[20] Through the 1970s, the lineup was constantly improved with new models that remained compatible in software and expansion with the original 2116.

In 1971, the updated 2100A replaced the entire existing 211x lineup. The overall system was similar to the earlier models and continued to be based on core memory. Physically it most resembled the 2114, as the power supply was built-in and it had limited internal expansion. However, the CPU was rebuilt with microcode that could be user programmed, and it added a memory protection system. An optional floating point unit was also available. These models were extremely successful, with over 8,000 sold by the time they were declared obsolete in 1978.^[1]

By 1972, HP had shipped 4,500 minis, making it one of the largest companies in the market. That year, they merged the Mountain View Division, which made magnetic tape drives, with the Cupertino Division to create the Data Systems Division (DSD). By this time, the HP 3000 project was in serious trouble, and in February 1973, Packard sent Paul Ely to take over the division. Sales of the 2100 series remained strong; the 6000th shipped in August 1973, the 8000th in February 1974, and its 10,000th in February 1975.^[21]

21MX

In 1972, the division decided to move to 4kbit SRAM memory chips in place of core. These were about twice as fast as contemporary low-cost core, and much smaller, allowing 32kword machines to be built in a 2114-like form factor. At the time they made this decision, 4kbit SRAMs were not actually available, so experimental machines using the core from a 2100 series were used initially, replaced by 1kbit SRAM. At first it appeared 4k parts would not be available by the time the rest of the machine had been upgraded, so the company canvassed various manufacturers and found that a few were aggressively developing 4k parts. In particular, Intel, Mostek, Motorola and Texas Instruments were all suggesting such parts would be available in quantity by late 1974.^[22]

Using such memories in an expansion chassis like the earlier systems meant there was room for much more memory, into the megaword range. However, the CPU's use of 15-bit addresses limited the size to 32kwords. To address the desire for larger systems, HP developed the "Dynamic Mapping System", or DMS. DMS expanded the address format from 15 to 20 bits, allowing a maximum of 1,048,576 words, a dramatic expansion of the original system.^[23]

These changes led to the 1974 introduction of the first of the 21MX series machines. This stood for the "21-M" processor and the "21-X" memory, as the memory control systems were separated from the CPU in order to provide flexibility in case the chosen 4k parts were changed during production. This proved useful in practice as the machines were shipped with memories using either Motorola or Texas Instruments parts, and they could be mixed in a single machine, while the higher density system based on 16-pin Mostek parts could be supported by replacing the normal 21-X/2 controller with the 21-X/1.^[22]

The entire 2100 series was replaced in 1974 with the first of these 21MX series machines. Using the highest-density parts, the new machines could support up to 1.2 MB in the largest models. When the CPU was further upgraded in 1976, the new models became the "21MX E-Series" and the original models retroactively became the "21MX M-Series". The main difference between the M and E was that the E used clever timing to improve the speed to about twice that of the M.^[24] A wider variety of machine styles were released as part of the 21MX series, including smaller systems with four slots and larger ones with 9 or 14 slots.^[25]

1000 series

An HP 2647A graphics terminal connected to an HP 1000 E-Series machine.

At the end of 1977, the entire line was renamed as the "HP 1000", becoming the "HP 1000 M-Series" and "HP 1000 E-Series". The next year the "HP 1000 F-Series" was introduced, which was an E-Series with an added floating point unit.^[26] By 1978, the success of the line had propelled HP to become the fourth largest manufacturer in the minicomputer space, trailing only DEC, IBM, and Data General.^[5]

In 1980, the "HP 1000 L-Series" was introduced. This used a new processor based on HP's large scale integration silicon on sapphire process. Additionally, the expansion cards were also equipped with their own processors that allowed them to access main memory and conduct input/output without bothering the CPU. Although this made the expansion cards incompatible with the earlier models for the first time, it also greatly improved overall performance. These models lacked the memory management unit.^[27]

The L-Series was itself replaced in 1982 with the "HP 1000 A-Series", which included a new "Lightning" CPU design that reached 1 MIPS, and the even faster "Magic" CPU at 3 MIPS. A wide variety of different models were produced, including desk-side towers, and a variety of different size rack-mount systems.^[27] A low-end A400 model was introduced in 1986,^[28] and the final high-end A990 released in 1990.^[29]

Memory organization

The HP 2100 was designed in an era when RAM in the form of core was falling from dollars to pennies per bit,^[30] while implementing processor registers using transistors or small scale integration was much more expensive. This favored designs with few registers and most storage in RAM, which in turn influenced the instruction set architecture (ISA) to use a memory-memory or memory-accumulator design. This basic concept was first widely introduced in the seminal 12-bit PDP-8, which spawned many similar designs like the 2100.

In the 2100, addresses were 15-bits long, allowing a total of 32k 16-bit words of memory (64kB in modern terms).^[31] The smallest addressable unit of memory was a 16-bit word, there were no instructions that fetched a single 8-bit byte. The address was broken into two parts, the 5 most significant bits referred to one of 32 "pages", while the 10 least significant bits were the "displacement" pointing to a single word within the 1,024 word page. With the DMS system in the 21MX series, the upper 5 bits were instead used to select one of 32 registers, each of which held 12 bits. The least significant 10 bits of the register were then placed in front of the original 10-bit displacement to produce a 20-bit address.^[23] The two most significant bits were used to implement memory protection.^[23]

Most processing was handled in the two A and B registers, each 16-bits wide. The registers were also accessible at memory locations 0 and 1, respectively. This meant that one could load a value into an accumulator using the normal register-save operation, for instance, LDA 1 would LoaD the value of the A register into memory location 1, thereby copying the value of A into B.^[32]

In addition to the A and B registers, the CPU also included the M register which holds the current memory address, and the T register which holds the value at that address.^[33] The P register was used as the program counter and automatically incremented with every instruction, but it was also used as the base address for some memory accesses (see below) that would be calculated and placed in M. There were also two one-bit registers, Overflow and Extend.^[31] Additionally, there was the S(witch)/D(isplay) register, which was used for input and output from the front panel.^[34][35]

Certain areas of memory were reserved for special purposes, like locations 0 and 1 used by the accumulators. Additional words in the lowest 64-locations in memory were used for direct memory access (DMA), and vectored interrupts (see below). In later models, the highest 64 words of available memory were reserved for the boot loader.^[36]

Instructions

The original instruction set contained 68^[5] or 70 instructions.^[37]

• Arithmetic — Add, Increment, And, Or, Exclusive-or
• Program Control — Skip, Jump, Jump to Subroutine
• Shift and Rotate — Arithmetic and Logical Shifts, 16- and 17-bit Rotates
• Optional — Multiply, Divide, 32-bit Load and Store, 32-bit Shifts

All 68 instructions in the standard instruction set were 16 bits long. Most executed in one memory cycle, or 16 clock cycles,^[38] although indirect addressing and the ISZ could use up to 36 cycles.^[34] Conditional branching was done with a conditional skip-over-one instruction, that one instruction normally being a jump instruction. There was no stack for subroutines; instead, the first memory location of the routine was reserved, and the return address written to that location by the JSB instruction.^[39] This means there is no internal support for re-entrant code; support for this has to be added via a user implemented stack.

There were three basic styles of instructions in the ISA; memory references, register references, and input/output. Certain models extended the ISA with add-on hardware, adding, for instance, floating point instructions or additional integer math and memory instructions, but these would fall into the same three basic categories.^[32]

Memory instructions used four bits for the instruction, and two more for special flags, for a total of six bits of the 16-bit word. This left room for a 10-bit address in the instruction, stored in the least significant bits (LSBs), 0 to 9. If bit 15 was set, this indicated "indirect" addressing instead of "direct". In Direct mode, the address in the instruction was the address of the operand, while in Indirect mode, the address was a pointer to another memory location that contained the address of the operand. One could set bit 15 on that location as well, allowing the indirection to be of any required depth, ending when one of the locations has a 0 in bit 15.^[31][40]

In addition to the Direct/Indirect mode, bit 10 of the instruction controlled the Z/C flag. When set to 0, this meant the address's upper five bits were zero while the lower 10 were the value in the instruction. This allowed fast access to the Z(ero) page, the first 1,024 words of memory. When set to 1, the address was constructed by combining the 10 bits in the instruction to the top 5 bits of the P register, the C(urrent) page of memory, allowing memory to be accessed as 32 pages of 1024 words.^[41] Thus 2,048 words could be addressed at any given time; 1,024 of them within page zero and another 1,024 within the same page as the instruction performing the reference.^[40]

Register instructions did not require an address, and thus had more free bits to work with. This was used to pack up four or eight instructions into a single memory word,^[42] which, used properly, could significantly speed operations. A total of 39 register operations were included, which were broken down into shift-and-rotate instructions, and the alter-and-skip instructions, indicated by bit 10,^[43] while bit 11 indicated whether this was being applied to register A or B.^[44]

There were two general classes of register instructions, the shift-and-rotate group and the alter-and-skip. The first was used for basic bitwise manipulation of the values in a register and could have up to four instructions per word, although the two instructions in the middle were always a CLE,SLA/B (clear E, skip if A/B is zero). The second group had eight instructions that performed increments on the registers and then a conditional branch. These were normally used to implement loops.^[43]

I/O and interrupts

Input/Output instructions normally communicated through the accumulators. The instruction format started with the bits "1000" in the most significant bits, followed by a single bit indicating which register to use (A=0, B=1), followed by a "1", the H/C flag bit, and then three bits for the instruction and the remaining six bits for the I/O device ID,^[45] or channel, allowing up to 64 devices. Some device numbers were used by the system itself.^[46]

I/O was initiated by clearing the Flag bit with STF and then setting the C bit using STC. The hardware would notice this pattern and begin its operation. When the operation was complete, the device would set the Flag bit and then the program would load the resulting data from the card using the LI* instruction, or send it to the card with OT*.^[45]

The actual data transfer was normally accomplished using the interrupt system. Memory locations 4 through 63 (decimal) held the addresses of routines to jump to when an interrupt was fired, providing 60 interrupt levels.^[47] Location 4 through 7 were hard-wired to power failures, parity check errors, and in later models memory protection errors. Locations 8 and up were user-accessible interrupt vectors, mapped to an I/O channel and arranged in priority order.^[48] So if I/O device 13 produced an interrupt, the CPU would jump to the location in memory location 13, but only if it was not masked out by a higher-priority interrupt, 1 to 12.^[47]

Another key feature of the 2100 series was a separate direct memory access controller that used cycle stealing to access memory when the CPU was not using it, during the times when it was performing internal calculations for instance. Using this feature, lengthy I/O processes could be completed while the CPU worked on other problems. The system was set up by sending an instruction to the DMA controller using the I/O commands; the DMA controller was channel 6, and was initially sent an instruction containing the number of the I/O device that wanted to use DMA, whether it was an input (write to memory from device) or output (read from memory to device), the starting location in memory for the data, and the number of words. This setup code was often installed into one of the interrupt vectors, automating the process.^[46] The DMS had separate tables for the CPU and DMA system, so DMA could load data into separate parts of extended memory.^[23]

Programming

HP supplied a three-pass assembler for the machine,^[49] using a column-delimited format. The first area, on the left of the line of code, was the label, which had to start in column 1 if present. Next came the instruction mnemonic, then the parameters. The assembler allows basic mathematical expressions to be written directly, instead of using mnemonics, and also included a number of pseudo-instructions like ORG to set the base address of the program. The rest of the line could be used for a comment.^[45]

In addition to the assembler and associated linker, the machines initially shipped with a FORTRAN 66 compiler, the operating system, and I/O drivers. Over time, additional languages were added including BASIC, ALGOL, FORTRAN IV^[50] and FORTRAN 77.^[51]

Operating systems

The 2100s were normally used with the "Real Time Executive" operating system, or RTE for short.^[52] Several versions of RTE were released for the different versions of the machine; RTE-II for the 2114-2116, RTE-III for the 2100s, RTE-IV for the 21MX series, and RTE-A for the "A" series.

The operating system shell, even in the late 1970s, was very primitive, with a single-level file system, File Manager, or FMGR. For example, the command to run a FORTRAN compiler would be as follows:^[51]

ru, f77, &test,'test,%test

meaning run the f77 program, using special characters to distinguish between source file, object, and executable files.

The HP 1000 also was one of the few minicomputers that restricted file names to only five characters, rather than the six common at the time, which made porting and even writing programs a challenge. The later RTE-A for HP 1000 provided conventional directory structure with 16.4 file names, and made the ru command optional.

GRAPHICS/1000 was a FORTRAN 5 character name implementation of AGL, which was based on the HP 9830 graphics commands.

Alternatively, a specific dual processor configuration was sold (the HP 2000 series, later known as HP 2000/Access) which could run HP Time-Shared BASIC. In the original system (2000A), a well-equipped 2116 acted as the main processor while a 2114 acted as the communications multiplexer, simulating many UART channels in software. In the last version, the 2000F, a 2100S and 2100A CPU were used, with the 2100A connected to up to 32 serial terminals via serial multiplexer interfaces.

TODS (Test Oriented Disk System) was developed by a technician at the HP board repair center to improve turn around time in the center. It was used to load diagnostics from a central repository as opposed to loading individual paper tapes. TODS was also used on HP 2116 thru 21MX-F series for test systems for missiles such as Phoenix (9206B), Harpoon (9500D-354), Tomahawk and many others. Early test sets were the 9500A evolving to the 9500D, followed by the ATS (Automated Test System). Specific HP test systems such as the 9500D-A46 Minuteman launch component test set and ATS-E35 Peacekeeper/Minuteman launch component test set. The HP 8580/8542 Microwave ANA/ASA (Automatic Network Analyzer / Automated Spectrum Analyzer) ran on TODS. The TDRSS microwave transponder test set used TODS and was a very large system.

There was also MTOS (Magnetic Tape Operating System) similar to TODS.

Early models (1966-1970)

These are the original models using core memory and a hardwired CPU.

• 2116A, 10 MHz clock, 1.6 microsecond (µs) cycle time. Normally supplied with 4kwords, expandable to 8k internally or 16k with an external memory system. Chassis includes 16 I/O slots, also expandable. Introduced November 1966.
• 2116B, supported a new 32k memory expansion option. Introduced September 1968.
• 2116C, used smaller core so a full 32k could fit in the main chassis. Introduced October 1970.
• 2115A, short-lived cost-reduced version that removed the DMA and some math functions, had only 8 I/O slots, and ran at 8 MHz clock and a 2.0 µs cycle time. Required a bulky external power supply. Introduced November 1967.
• 2114A, further simplified 2115 with a new front panel and internal power supply. Introduced October 1968.
• 2114B, 2114A with a single DMA channel and a new front panel with illuminated push-buttons. Introduced November 1969.
• 2114C, as 2114B with a maximum 16k memory. Introduced October 1970.
• HP 2000A, combined 2116A and several upgrades and I/O devices. Introduced November 1968.

Second generation (1970-1974)

Core memory, microprogrammed CPU with hardware multiply and divide. A simple memory protection system caused a high-priority interrupt when triggered. Included a two-channel DMA controller for higher throughput. A floating-point processor was an option, as was user microprogramming. Front panel buttons were illuminated by small incandescent lamps that burned out with use. The use of a switched-mode power supply^{[lower-alpha 2]} allowed the chassis to be significantly smaller than the earlier models.

• 2100A, normally with 4k but expandable to 32k, 14 I/O slots expandable to 45. Introduced in 1971.
• 2100S, 2100A bundled with the floating-point option, a time base generator for interfacing with time-dependant hardware, and a teleprinter interface card. Introduced in 1973.

21MX (1975-1979)

The 21MX series featured a memory management unit and semiconductor memory expandable to 1,048,576 words (one megaword). The bit displays on the front panel buttons used small red LEDs, instead of the incandescent bulbs used in earlier versions.

• M-series — 2105A, 2108A, 2112A (blue line on front panel)
• E-series — 2109A, 2113A (yellow line on front panel; E for Extended)
• F-series — 2111F, 2117F (red line on front panel; F for Floating point Processor in a separate 2U chassis)

The 21MX ran the HP RTE (Real Time) Operating System (OS). They started out as refrigerator-sized 19-inch rackmount systems with lights and switches on the front panels. The last models would use a 1-chip processor and fit under a desk using a console terminal rather than a front panel.

The new L and A series models had HP-IB interface ability, but as with all HP systems at that time, the blinking LED lights were removed from the front panel. Despite customer demands for a real-time ability and HP R&D's efforts using an installable real-time card, the RTE-A OS was not as good at real-time operations as RTE on a 21MX. This was an important reason this computer was hard to kill. Many companies use real-time operations to take a measurements and control processes — turn on or off a pump, heater, a valve, speed up or slow down a motor, etc.

L-Series (1980)

• HP1000L SOS (silicon on sapphire) CPU and I/O processors

A-Series (1981-1996)

Each addressable up to 32 MB of RAM.

1981:

• A600 - based on Am2900 bit-slice processor, 1 MIPS, 53kFLOPS
• A600+ - based on Am2900 bit-slice processor, supports code and data separation, optional ECC (error correcting) memory. Codename: LIGHTNING

1982??:

• A700 - based on AMD AM2903 bit-slice processor, optional hardware floating point processor, 1MIPS, 204kFLOPS, microprogramming, optional ECC memory. Codename: PHOENIX

1984:

• A900 - Provides pipelined data path, 3MIPS, 500kFLOPS, ECC memory. Codename MAGIC

1986:

• A400 - first single-board CPU including 4 serial lines; CPU fabricated by VLSI Technology with their CMOS-40 process, 512kB RAM on board. Codename Yellowstone

1992:

• A990 - CPU implemented with two 208-pin CMOS application-specific integrated circuits (ASICs), 298 instructions, supports up to 512 MB of memory.

Citations

Bibliography

• Leibson, Steve (2017). "HP: The Accidentally, On-Purpose Computer Company". HP9825.COM.
• The Hewlett Packard Company. HP1000/RTE Home page.
• Hewlett-Packard (March 1967). "Section 2-26, Direct/Indirect". HP 2116A Computer Specifications and Basic Operation, Volume 1 (PDF). pp. 2–3.
• Peterson, James (2014). "Section 2-26, Direct/Indirect". Computer Organization and Assembly Language Programming. Academic Press. pp. 369–378.
• Guide to the 2100 Computer. Hewlett-Packard. September 1972.
• Frankenberg, Robert (October 1974). "All Semiconductor Memory Selected for New Minicomputer Series". Hewlett-Packard Journal.