List of ARM microarchitectures

This is a list of microarchitectures based on the ARM family of instruction sets designed by ARM Holdings and 3rd parties, sorted by version of the ARM instruction set, release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design.[1] Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

ARM cores

Designed by ARM

ARM family ARM architecture ARM core Feature Cache (I / D), MMU Typical MIPS @ MHz Reference
ARM1 ARMv1 ARM1 First implementation None
ARM2 ARMv2 ARM2 ARMv2 added the MUL (multiply) instruction None 4 MIPS @ 8 MHz
0.33 DMIPS/MHz
ARMv2a ARM250 Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions None, MEMC1a 7 MIPS @ 12 MHz
ARM3 ARMv2a ARM3 First integrated memory cache 4 KB unified 12 MIPS @ 25 MHz
0.50 DMIPS/MHz
ARM6 ARMv3 ARM60 ARMv3 first to support 32-bit memory address space (previously 26-bit).
ARMv3M first added long multiply instructions (32x32=64).		 None 10 MIPS @ 12 MHz
ARM600 As ARM60, cache and coprocessor bus (for FPA10 floating-point unit) 4 KB unified 28 MIPS @ 33 MHz
ARM610 As ARM60, cache, no coprocessor bus 4 KB unified 17 MIPS @ 20 MHz
0.65 DMIPS/MHz		 [4]
ARM7 ARMv3 ARM700 8 KB unified 40 MHz
ARM710 As ARM700, no coprocessor bus 8 KB unified 40 MHz [5]
ARM710a As ARM710 8 KB unified 40 MHz
0.68 DMIPS/MHz
ARM7T ARMv4T ARM7TDMI(-S) 3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing None 15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
ARM710T As ARM7TDMI, cache 8 KB unified, MMU 36 MIPS @ 40 MHz
ARM720T As ARM7TDMI, cache 8 KB unified, MMU with FCSE (Fast Context Switch Extension) 60 MIPS @ 59.8 MHz
ARM740T As ARM7TDMI, cache MPU
ARM7EJ ARMv5TEJ ARM7EJ-S 5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructions None
ARM8 ARMv4 ARM810 5-stage pipeline, static branch prediction, double-bandwidth memory 8 KB unified, MMU 84 MIPS @ 72 MHz
1.16 DMIPS/MHz		 [6][7]
ARM9T ARMv4T ARM9TDMI 5-stage pipeline, Thumb None
ARM920T As ARM9TDMI, cache 16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension) 200 MIPS @ 180 MHz [8]
ARM922T As ARM9TDMI, caches 8 KB / 8 KB, MMU
ARM940T As ARM9TDMI, caches 4 KB / 4 KB, MPU
ARM9E ARMv5TE ARM946E-S Thumb, enhanced DSP instructions, caches Variable, tightly coupled memories, MPU
ARM966E-S Thumb, enhanced DSP instructions No cache, TCMs
ARM968E-S As ARM966E-S No cache, TCMs
ARMv5TEJ ARM926EJ-S Thumb, Jazelle DBX, enhanced DSP instructions Variable, TCMs, MMU 220 MIPS @ 200 MHz
ARMv5TE ARM996HS Clockless processor, as ARM966E-S No caches, TCMs, MPU
ARM10E ARMv5TE ARM1020E 6-stage pipeline, Thumb, enhanced DSP instructions, (VFP) 32 KB / 32 KB, MMU
ARM1022E As ARM1020E 16 KB / 16 KB, MMU
ARMv5TEJ ARM1026EJ-S Thumb, Jazelle DBX, enhanced DSP instructions, (VFP) Variable, MMU or MPU
ARM11 ARMv6 ARM1136J(F)-S 8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions Variable, MMU 740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz [9]
ARMv6T2 ARM1156T2(F)-S 9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructions Variable, MPU [10]
ARMv6Z ARM1176JZ(F)-S As ARM1136EJ(F)-S Variable, MMU + TrustZone 965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors [11]
ARMv6K ARM11MPCore As ARM1136EJ(F)-S, 1–4 core SMP Variable, MMU
SecurCore ARMv6-M SC000 0.9 DMIPS/MHz
ARMv4T SC100
ARMv7-M SC300 1.25 DMIPS/MHz
Cortex-M ARMv6-M Cortex-M0[12] Microcontroller profile, most Thumb + some Thumb-2,[13] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory Optional cache, no TCM, no MPU 0.84 DMIPS/MHz
Cortex-M0+[14] Microcontroller profile, most Thumb + some Thumb-2,[13] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory Optional cache, no TCM, optional MPU with 8 regions 0.93 DMIPS/MHz
Cortex-M1[15] Microcontroller profile, most Thumb + some Thumb-2,[13] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory Optional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU 136 DMIPS @ 170 MHz,[16] (0.8 DMIPS/MHz FPGA-dependent)[17]
ARMv7-M Cortex-M3[18] Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory Optional cache, no TCM, optional MPU with 8 regions 1.25 DMIPS/MHz
ARMv7E-M Cortex-M4[19] Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory Optional cache, no TCM, optional MPU with 8 regions 1.25 DMIPS/MHz (1.27 w/FPU)
Cortex-M7[20] Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions 0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions 2.14 DMIPS/MHz
Cortex-R ARMv7-R Cortex-R4[21] Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 8/12 regions 1.67 DMIPS/MHz[22]
Cortex-R5[23] Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)[24] 0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions 1.67 DMIPS/MHz[22]
Cortex-R7[25] Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP[24] 0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt. MPU with 16 regions 2.50 DMIPS/MHz[22]
Cortex-R8[26] TBD TBD 2.50 DMIPS/MHz[22]
Cortex-A
(32-bit)		 ARMv7-A Cortex-A5[27] Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 4−64 KB / 4−64 KB L1, MMU + TrustZone 1.57 DMIPS/MHz per core
Cortex-A7[28] Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design[29] 8−64 KB / 8−64 KB L1, 0–1 MB L2, MMU + TrustZone 1.9 DMIPS/MHz per core
Cortex-A8[30] Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline 16–32 KB / 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU + TrustZone Up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
Cortex-A9[31] Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 16–64 KB / 16–64 KB L1, 0–8 MB L2 opt. parity, MMU + TrustZone 2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual-core)
Cortex-A12[32] Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 32−64 KB 3.0 DMIPS/MHz per core
Cortex-A15[33] Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[29] 32 KB w/parity / 32 KB w/ECC L1, 0–4 MB L2, L2 has ECC, MMU + TrustZone At least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation)[34]
Cortex-A17[35] Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP 32 KB L1, 256 KB–8 MB L2 w/optional ECC 2.8 DMIPS/MHz
ARMv8-A Cortex-A32[36] Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline 8–64 KB w/optional parity / 8−64 KB w/optional ECC L1 per core, 128 KB–1 MB L2 w/optional ECC shared
Cortex-A
(64-bit)		 ARMv8-A Cortex-A35[37] Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses 1.78 DMIPS/MHz
Cortex-A53[38] Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline 8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–2 MB L2 shared, 40-bit physical addresses 2.3 DMIPS/MHz
Cortex-A57[39] Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-way superscalar, deeply out-of-order pipeline 48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses 4.1 - 4.5 DMIPS/MHz[40][41]
Cortex-A72[42] Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-way superscalar, deeply out-of-order pipeline 48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses 4.7 DMIPS/MHz
Cortex-A73[43] Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-way superscalar, deeply out-of-order pipeline 64 KB / 32−64 KB L1 per core, 256 KB–8 MB L2 shared w/ optional ECC, 44-bit physical addresses 4.8 DMIPS/MHz[44]
ARMv8.2-A Cortex-A55[45] Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, triple issue, in-order pipeline[46] 64 / 64 kB L1, 256 kB L2 per core, 4 MB L3 shared
Cortex-A75[47] Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-way superscalar, deeply out-of-order pipeline[48] 64 / 64 kB L1, 512 kB L2 per core, 4 MB L3 shared
ARM family ARM architecture ARM core Feature Cache (I / D), MMU Typical MIPS @ MHz Reference

As Dhrystone is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

Designed by third parties

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

Core Family Instruction set Microarchitecture Feature Cache (I / D), MMU Typical MIPS @ MHz
StrongARM
(Digital)		 ARMv4 SA-110 5-stage pipeline 16 KB / 16 KB, MMU 100–233 MHz
1.0 DMIPS/MHz
SA-1100 derivative of the SA-110 16 KB / 8 KB, MMU
Faraday[49]
(Faraday Technology)		 ARMv4FA5106-stage pipelineUp to 32 KB / 32 KB cache, MPU1.26 DMIPS/MHz
100–200 MHz
FA526Up to 32 KB / 32 KB cache, MMU1.26 MIPS/MHz
166–300 MHz
FA6268-stage pipeline32 KB / 32 KB cache, MMU1.35 DMIPS/MHz
500 MHz
ARMv5TEFA606TE5-stage pipelineNo cache, no MMU1.22 DMIPS/MHz
200 MHz
FA626TE8-stage pipeline32 KB / 32 KB cache, MMU1.43 MIPS/MHz
800 MHz
FMP626TE8-stage pipeline, SMP1.43 MIPS/MHz
500 MHz
FA726TE13 stage pipeline, dual issue2.4 DMIPS/MHz
1000 MHz
XScale
(Intel / Marvell)		 ARMv5TE XScale 7-stage pipeline, Thumb, enhanced DSP instructions 32 KB / 32 KB, MMU 133–400 MHz
Bulverde Wireless MMX, wireless SpeedStep added 32 KB / 32 KB, MMU 312–624 MHz
Monahans[50] Wireless MMX2 added 32 KB / 32 KB L1, optional L2 cache up to 512 KB, MMU Up to 1.25 GHz
Sheeva
(Marvell)		 ARMv5Feroceon5–8 stage pipeline, single-issue16 KB / 16 KB, MMU600–2000 MHz
Jolteon5–8 stage pipeline, dual-issue32 KB / 32 KB, MMU
PJ1 (Mohawk)5–8 stage pipeline, single-issue, Wireless MMX232 KB / 32 KB, MMU1.46 DMIPS/MHz
1.06 GHz
ARMv6 / ARMv7-APJ46–9 stage pipeline, dual-issue, Wireless MMX2, SMP32 KB / 32 KB, MMU2.41 DMIPS/MHz
1.6 GHz
Snapdragon
(Qualcomm)		 ARMv7-A Scorpion[51] 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide) 256 KB L2 per core 2.1 DMIPS/MHz per core
Krait[51] 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide) 4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core 3.3 DMIPS/MHz per core
ARMv8-A Kryo[52] 4 cores.?Up to 2.2 GHz

(6.3 DMIPS/MHz)

Ax
(Apple)		 ARMv7-A Swift[53] 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON L1: 32 KB / 32 KB, L2: 1 MB 3.5 DMIPS/MHz per core
ARMv8-ACyclone[54]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 1 MB, L3: 4 MB1.3–1.4 GHz
ARMv8-ATyphoon[54][55]2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 1 or 2 MB, L3: 4 MB1.4−1.5 GHz
ARMv8-ATwister[56]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 2 MB, L3: 4 MB or 0 MB1.85 or 2.26 GHz
ARMv8-A Hurricane[57]2 or 3 cores. AArch64, 6-decode, 6-issue, 9-wide, superscalar, out-of-orderL1: 64 KB / 64 KB, L2: 3 or 8 MB, L3: 4 or 0 MB2.34 or 2.38 GHz
X-Gene
(Applied Micro)		 ARMv8-AX-Gene64-bit, quad issue, SMP, 64 cores[58]Cache, MMU, virtualization3 GHz (4.2 DMIPS/MHz per core)
Denver
(Nvidia)		 ARMv8-ADenver[59][60]2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128 MB optimization cache,
Denver1: 28nm, Denver2:16nm		128 KB I-cache / 64 KB D-cacheUp to 2.5 GHz
Carmel
(Nvidia)		 ARMv8(t.b.d.)Carmel[61][62]2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization, ? MB optimization cache,
functional safety, dual execution, parity & ECC		? KB I-cache / ? KB D-cacheUp to ? GHz
ThunderX
(Cavium)		 ARMv8-AThunderX64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips)?Up to 2.2 GHz
K12
(AMD)		 ARMv8-AK12[63]???
Exynos
(Samsung)		 ARMv8-AM1/M2 ("Mongoose")[64]4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB5.1 DMIPS/MHz

(2.6 GHz)

ARMv8-A M3 ("Meerkat")[65] 4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order64 KB I-cache / 32 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB?

ARM core timeline

The following table lists each core by the year it was announced.[66][67] Cores before ARM7 are not included.

Year Classic cores Cortex cores
ARM7ARM8ARM9ARM10ARM11MicrocontrollerReal-timeApplication
(32-bit)		Application
(64-bit)
1993 ARM700
1994 ARM710
ARM7DI
ARM7TDMI
1995 ARM710a
1996 ARM810
1997 ARM710T
ARM720T
ARM740T
1998 ARM9TDMI
ARM940T
1999 ARM9E-S
ARM966E-S
2000 ARM920T
ARM922T
ARM946E-S		ARM1020T
2001 ARM7TDMI-S
ARM7EJ-S		ARM9EJ-S
ARM926EJ-S		ARM1020E
ARM1022E
2002 ARM1026EJ-SARM1136J(F)-S
2003 ARM968E-SARM1156T2(F)-S
ARM1176JZ(F)-S
2004 Cortex-M3
2005 ARM11MPCoreCortex-A8
2006 ARM996HS
2007 Cortex-M1Cortex-A9
2008
2009 Cortex-M0Cortex-A5
2010 Cortex-M4(F)Cortex-A15
2011 Cortex-R4
Cortex-R5
Cortex-R7		Cortex-A7
2012 Cortex-M0+Cortex-A53
Cortex-A57
2013 Cortex-A12
2014 Cortex-M7(F)Cortex-A17
2015 Cortex-A35
Cortex-A72
2016 Cortex-M23
Cortex-M33(F)		Cortex-R8
Cortex-R52		Cortex-A32Cortex-A73
2017 Cortex-A55
Cortex-A75
2018 Cortex-M35PCortex-A76

See also

References

  1. ↑ "ARM Powered Standard Products" (PDF). 2005. Retrieved 23 December 2017.
  2. ↑ ARM Ltd and ARM Germany GmbH. "Device Database". Keil. Retrieved 6 January 2011.
  3. ↑ "Processors". ARM. 2011. Retrieved 6 January 2011.
  4. ↑ "ARM610 Datasheet". ARM Holdings. August 1993. Archived from the original (PDF) on July 3, 2016. Retrieved July 5, 2017.
  5. ↑ "ARM710 Datasheet". ARM Holdings. July 1994. Archived from the original (PDF) on July 3, 2016. Retrieved July 5, 2017.
  6. ↑ ARM Holdings (7 August 1996). "ARM810 – Dancing to the Beat of a Different Drum" (PDF). Hot Chips. Retrieved 21 September 2013.
  7. ↑ "VLSI Technology Now Shipping ARM810". EE Times. 26 August 1996. Retrieved 21 September 2013.
  8. ↑ Register 13, FCSE PID register ARM920T Technical Reference Manual
  9. ↑ "ARM1136J(F)-S – ARM Processor". Arm.com. Archived from the original on 21 March 2009. Retrieved 18 April 2009.
  10. ↑ https://www.arm.com/products/processors/classic/arm11/arm1156.php
  11. ↑ "ARM11 Processor Family". ARM. Retrieved 12 December 2010.
  12. ↑ Cortex-M0 Specification Summary; ARM Holdings.
  13. 1 2 3 Cortex-M0/M0+/M1 Instruction set; ARM Holding.
  14. ↑ Cortex-M0+ Specification Summary; ARM Holdings.
  15. ↑ Cortex-M1 Specification Summary; ARM Holdings.
  16. ↑ "ARM Extends Cortex Family with First Processor Optimized for FPGA" (Press release). ARM Holdings. 19 March 2007. Retrieved 11 April 2007.
  17. ↑ "ARM Cortex-M1". ARM product website. Retrieved 11 April 2007.
  18. ↑ Cortex-M3 Specification Summary; ARM Holdings.
  19. ↑ Cortex-M4 Specification Summary; ARM Holdings.
  20. ↑ Cortex-M7 Specification Summary; ARM Holdings.
  21. ↑ Cortex-R4 Specification Summary; ARM Holdings.
  22. 1 2 3 4 Ltd., Arm. "Cortex-R – Arm Developer". ARM Developer. Retrieved 2018-03-29.
  23. ↑ Cortex-R5 Specification Summary; ARM Holdings.
  24. 1 2 Cortex-R5 & Cortex-R7 Press Release; ARM Holdings; 31 January 2011.
  25. ↑ Cortex-R7 Specification Summary; ARM Holdings.
  26. ↑ Cortex-R8 Specification Summary; ARM Holdings.
  27. ↑ Cortex-A5 Specification Summary; ARM Holdings.
  28. ↑ Cortex-A7 Specification Summary; ARM Holdings.
  29. 1 2 "Deep inside ARM's new Intel killer". The Register. 20 October 2011.
  30. ↑ Cortex-A8 Specification Summary; ARM Holdings.
  31. ↑ Cortex-A9 Specification Summary; ARM Holdings.
  32. ↑ Cortex-A12 Summary; ARM Holdings.
  33. ↑ Cortex-A15 Specification Summary; ARM Holdings.
  34. ↑ Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 | ITProPortal.com
  35. ↑ Cortex-A17 Specification Summary; ARM Holdings.
  36. ↑ "Cortex-A32 Processor". ARM Holdings. Retrieved 18 May 2016.
  37. ↑ "Cortex-A35 Processor". ARM Holdings. Retrieved 18 May 2016.
  38. ↑ "Cortex-A53 Processor". ARM Holdings. Retrieved 13 October 2012.
  39. ↑ "Cortex-A57 Processor". ARM Holdings. Retrieved 13 October 2012.
  40. ↑ "Cortex-Ax vs performance". Retrieved 5 May 2017.
  41. ↑ "Relative Performance of ARM Cortex-A 32-bit and 64-bit Cores". Retrieved 5 May 2017.
  42. ↑ "Cortex-A72 Processor". ARM Holdings. Retrieved 3 February 2015.
  43. ↑ "Cortex-A73 Processor". ARM Holdings. Retrieved 2 June 2016.
  44. ↑ "Cortex-Ax vs performance". Retrieved 5 May 2017.
  45. ↑ Ltd., Arm. "Cortex-A55 – Arm Developer". ARM Developer. Retrieved 2017-11-27.
  46. ↑ "Hardware.Info Nederland". nl.hardware.info (in Dutch). Retrieved 2017-11-27.
  47. ↑ Ltd., Arm. "Cortex-A75 – Arm Developer". ARM Developer. Retrieved 2017-11-27.
  48. ↑ "Hardware.Info Nederland". nl.hardware.info (in Dutch). Retrieved 2017-11-27.
  49. ↑ "Processor Cores". Faraday Technology.
  50. ↑ "3rd Generation Intel XScale Microarchitecture: Developer's Manual" (PDF). download.intel.com. Intel. May 2007. Retrieved 2 December 2010.
  51. 1 2 Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored; Anandtech.
  52. ↑ "Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute". Qualcomm. 2015-09-02. Retrieved 2015-09-06.
  53. ↑ Lal Shimpi, Anand (15 September 2012). "The iPhone 5's A6 SoC: Not A15 or A9, a Custom Apple Core Instead". AnandTech. Retrieved 15 September 2012.
  54. 1 2 Smith, Ryan (November 11, 2014). "Apple A8X's GPU - GAX6850, Even Better Than I Thought". Anandtech.
  55. ↑ Chester, Brandon (July 15, 2015). "Apple Refreshes The iPod Touch With A8 SoC And New Cameras". Anandtech. Retrieved September 11, 2015.
  56. ↑ Ho, Joshua (September 28, 2015). "iPhone 6s and iPhone 6s Plus Preliminary Results". Anandtech. Retrieved December 18, 2015.
  57. ↑ Ho, Joshua (September 28, 2015). "The iPhone 7 and iPhone 7 Plus Review". Anandtech. Retrieved September 14, 2017.
  58. ↑ http://www.pcworld.com/article/2464600/appliedmicros-64core-chip-could-spark-off-arm-core-war.html
  59. ↑ http://www.anandtech.com/Gallery/Album/3847
  60. ↑ http://blogs.nvidia.com/blog/2014/08/11/tegra-k1-denver-64-bit-for-android/
  61. ↑ https://www.golem.de/news/nvidia-drive-xavier-fuer-autonome-autos-wird-ausgeliefert-1801-132035.html
  62. ↑ https://wccftech.com/nvidia-drive-xavier-soc-detailed/
  63. ↑ http://www.anandtech.com/show/7990/amd-announces-k12-core-custom-64bit-arm-design-in-2016
  64. ↑ "Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU". AnandTech.
  65. ↑ "Hot Chips 2018: Samsung's Exynos-M3 CPU Architecture Deep Dive". AnandTech.
  66. ↑ ARM Company Milestones.
  67. ↑ ARM Press Releases.

Further reading

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