HiSilicon

The first well known product of HiSilicon is the K3V2 used in Huawei Ascend D Quad XL (U9510) smartphones[9] and Huawei MediaPad 10 FHD7 tablets. This chipset is based on the ARM Cortex-A9 MPCore fabbed at 40 nm and uses a 16 core Vivante GC4000 GPU.[10] The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

This is a revised version of K3V2 SoC with improved support of Intel baseband. The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

• supports – USB 2.0 / 13 MP / 1080p video encode

• DaVinci NPU based on Tensor Arithmetic Unit
• Kirin 820 supported 5G NSA & SA

• The Kirin 920 SoC also contains an image processor that supports up to 32-megapixel

• supports – SD 3.0 (UHS-I) / eMMC 4.51 / Dual-band a/b/g/n Wi-Fi / Bluetooth 4.0 Low Energy / USB 2.0 / 32 MP ISP / 1080p video encode

• supports – SD 4.1 (UHS-II) / UFS 2.0 / eMMC 5.1 / MU-MIMO 802.11ac Wi-Fi / Bluetooth 4.2 Smart / USB 3.0 / NFS / Dual ISP (42 MP) / Native 10-bit 4K video encode / i5 coprocessor / Tensilica HiFi 4 DSP

• Interconnect: ARM CCI-550, Storage: UFS 2.1, eMMC 5.1, Sensor Hub: i6

• Interconnect: ARM CCI-550, Storage: UFS 2.1, Sensor Hub: i7
• Cadence Tensilica Vision P6 DSP.[20]
• NPU made in collaboration with Cambricon Technologies. 1.92T FP16 OPS.[21]

It is HiSilicon's first SoC based on 7 nm FinFET technology.

• Interconnect: ARM Mali G76-MP10, Storage: UFS 2.1, Sensor Hub: i8
• Dual NPU made in collaboration with Cambricon Technologies.

It is HiSilicon's second 5G SoC based on 7 nm FinFET technology.

• Interconnect : ARM Mali-G77 MP8
• Big-Tiny Core Da Vinci NPU

Kirin 990 5G is HiSilicon's first SoC based on N7+ nm FinFET technology.[23]

• Interconnect: ARM Mali-G76 MP16
• Da Vinci NPU.
  • Kirin 990 4G: 1x Da Vinci Lite + 1x Da Vinci Tiny
  • Kirin 990 5G: 2x Da Vinci Lite + 1x Da Vinci Tiny
• Da Vinci Lite features 3D Cube Tensor Computing Engine (2048 FP16 MACs + 4096 INT8 MACs), Vector unit (1024bit INT8/FP16/FP32)
• Da Vinci Tiny features 3D Cube Tensor Computing Engine (256 FP16 MACs + 512 INT8 MACs), Vector unit (256bit INT8/FP16/FP32)[24]

The Balong 700 supports LTE TDD/FDD.[25] Its specs:

• 3GPP R8 protocol
• LTE TDD and FDD
• 4x2/2x2 SU-MIMO

At MWC 2012 HiSilicon released the Balong 710.[26] It is a multi-mode chipset supporting 3GPP Release 9 and LTE Category 4 at GTI (Global TD-LTE Initiative). The Balong 710 was designed to be used with the K3V2 SoC. Its specs:

• LTE FDD mode : 150 Mbit/s downlink and 50 Mbit/s uplink.
• TD-LTE mode: up to 112 Mbit/s downlink and up to 30 Mbit/s uplink.
• WCDMA Dual Carrier with MIMO: 84Mbit/s downlink and 23Mbit/s uplink.

The Balong 720 supports LTE Cat6 with 300 Mbit/s peak download rate.[25] Its specs:

• TSMC 28 nm HPM process
• TD-LTE Cat.6 standard
• Dual-carrier aggregation for the 40 MHz bandwidth
• 5-mode LTE Cat6 Modem

The Balong 750 supports LTE Cat 12/13, and it is first to support 4CC CA and 3.5 GHz.[25] Its specs:

• LTE Cat.12 and Cat.13 UL network standards
• 2CC (dual-carrier) data aggregation
• 4x4 multiple-input multiple-output (MIMO)
• TSMC 16 nm FinFET+ process

The Balong 765 supports 8×8 MIMO technology, LTE Cat.19 with downlink data-rate up to 1.6 Gbit/s in FDD network and up to 1.16 Gbit/s in the TD-LTE network.[27] Its specs:

• 3GPP Rel.14
• LTE Cat.19 Peak data rate up to 1.6 Gbit/s
• 4CC CA + 4×4 MIMO/2CC CA + 8×8 MIMO
• DL 256QAM
• C-V2X

The Balong 5G01 supports the 3GPP standard for 5G with downlink speeds of up to 2.3 Gbit/s. It supports 5G across all frequency bands including sub-6 GHz and millimeter wave (mmWave).[25] Its specs:

• 3GPP Release 15
• Peak data rate up to 2.3 Gbit/s
• Sub 6 GHz and mmWave
• NSA/SA
• DL 256QAM

The Balong 5000 supports supports 2G, 3G, 4G, and 5G.[28] Its specs:

• 2G/3G/4G/5G Multi Mode
• Fully compliant with 3GPP Release 15
• Sub-6 GHz: 100 MHz x 2CC CA
• Sub-6 GHz:Downlink up to 4.6 Gbit/s, Uplink up to 2.5 Gbit/s
• mmWave:Downlink up to 6.5 Gbit/s, Uplink up to 3.5 Gbit/s
• NR+LTE:Downlink up to 7.5 Gbit/s
• FDD & TDD Spectrum Access
• SA & NSA Fusion Network Architecture
• Supports 3GPP R14 V2X
• 3GB LPDDR4X[29]

The Kirin A1 was announced on September 6, 2019.[30] It features:

• BT/BLE dual-mode Bluetooth 5.1[31]
• Isochronous Dual Channel transmission technology
• 356 MHz audio processor

The Hi1610 is HiSilicon's first generation server processor announced in 2015. It features:

• 16x ARM Cortex-A57 at up to 2.1 GHz[32]
• 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 16MB CCN L3
• TSMC 16 nm
• 2x DDR4-1866
• 16 PCIe 3.0

The Hi1612 is HiSilicon's second generation server processor launched in 2016. It features:

• 32x ARM Cortex-A57 at up to 2.1 GHz[32]
• 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 32MB CCN L3
• TSMC 16 nm
• 4x DDR4-2133
• 16 PCIe 3.0

The Kunpeng 916 (formally known as Hi1616) is HiSilicon's third generation server processor launched in 2017. The Kunpeng 916 is utilized in Huawei's TaiShan 2280 Balanced Server, TaiShan 5280 Storage Server, TaiShan XR320 High-Density Server Node and TaiShan X6000 High-Density Server.[33][34][35][36] It features:

• 32x Arm Cortex-A72 at up to 2.4 GHz[32]
• 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 32MB CCN L3
• TSMC 16 nm
• 4x DDR4-2400
• 2-way Symmetric multiprocessing (SMP), Each socket has 2x ports with 96 Gbit/s per port (total of 192 Gbit/s per each socket interconnects)
• 46 PCIe 3.0 and 8x 10 GbE
• 85 W

The Kunpeng 920 (formally known as Hi1620) is HiSilicon's fourth generation server processor announced in 2018, launched in 2019. Huawei claim the Kunpeng 920 CPU scores more than an estimated 930 on SPECint®_rate_base2006.[37] The Kunpeng 920 is utilized in Huawei's TaiShan 2280 V2 Balanced Server, TaiShan 5280 V2 Storage Server and TaiShan XA320 V2 High-Density Server Node.[38][39][40] It features:

• 32 to 64x custom TaiShan v110 cores at up to 2.6 GHz.[41]
• The TaiShan v110 core is a 4-way out-of-order superscalar that implements the ARMv8.2-A ISA. Huawei reports the core supports almost all the ARMv8.4-A ISA features with a few exceptions, including dot product and the FP16 FML extension.[41]
• The TaiShan v110 cores are likely a new core not based off ARM designs [42]
• 3x Simple ALUs, 1x Complex MDU, 2x BRUs (sharing ports with ALU2/3), 2x FSUs (ASIMD FPU), 2x LSUs[42]
• 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1MB L3/core Shared.
• TSMC 7 nm HPC
• 8x DDR4-3200
• 2-way and 4-way Symmetric multiprocessing (SMP). Each socket has 3x Hydra ports with 240 Gbit/s per port (total of 720 Gbit/s per each socket interconnects)
• 40 PCIe 4.0 with CCIX support, 4 USB 3.0, 2x SATA 3.0, x8 SAS 3.0 and 2 x 100 GbE
• 100 to 200 W
• Compression engine (GZIP, LZS, LZ4) capable of up to 40 Gib/s compress and 100 Gbit/s decompress
• Crypto offload engine (for AES, DES, 3DES, SHA1/2, etc..) capable of throughputs up to 100 Gbit/s

The Kunpeng 930 (formally known as Hi1630) is HiSilicon's fifth-generation server processor announced in 2019 and scheduled for launch in 2021. It features:

• TBD custom cores with higher frequencies, support for simultaneous multithreading (SMT) and Arm's Scalable Vector Extension (SVE).[41]
• 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1MB L3/core Shared
• TSMC 7 nm?
• 8x DDR5

The Kunpeng 950 is HiSilicon's sixth-generation server processor announced in 2019 and scheduled for launch in 2023

Each Da Vinci Max AI Core features a 3D Cube Tensor Computing Engine (4096 FP16 MACs + 8192 INT8 MACs), Vector unit (2048bit INT8/FP16/FP32) and scalar unit. It includes a new AI framework called "MindSpore", a platform-as-a-service product called ModelArts, and a lower-level library called Compute Architecture for Neural Networks (CANN).[24]

The Ascend 310 is an AI inference SoC, it was codenamed Ascend-Mini. The Ascend 310 is capable of 16 TOPS@INT8 and 8 TOPS@FP16.[43] The Ascend 310 features:

• 2x Da Vinci Max AI cores[24]
• 8x ARM Cortex-A55 CPU cores
• 8MB On-chip buffer
• 16 Channel Video Decode – H.264/H.265
• 1 Channel Video Encode – H.264/H.265
• TSMC 12 nm FFC Process
• 8 W

The Ascend 910 is an AI training SoC, it was codenamed Ascend-Max. which delivers 256 TFLOPS@FP16 and 512 TOPS@INT8. The Ascend 910 features:

• 32x Da Vinci Max AI cores arranged in 4 clusters[24]
• 1024-bit NoC Mesh @ 2 GHz, with 128 GB/s bandwidth Read/Write per core
• 3x 240Gbit/s HCCS ports for Numa connections
• 2x 100Gbit/s RoCE interfaces for networking
• 4x HBM2E, 1.2 TB/s bandwidth
• 3D-SRAM stacked below AI SoC die
• 1228 mm² Total die size (456 mm² Virtuvian AI SoC, 168 mm² Nimbus V3 IO Die, 4x96mm ² HBM2E, 2x110 mm² Dummy Die)
• 32MB On-chip buffer
• 128 Channel Video Decode – H.264/H.265
• TSMC 7+ nm EUV (N7+) Process
• 350 W

The Ascend 910 Cluster has 1024–2048 Ascend 910 chips to reach 256–512 petaFLOPS@FP16. The Ascend 910 and Ascend Cluster will be available in Q2 2019.[44]