Cavium

On June 17, 2011, Cavium Networks, Inc. changed their name to Cavium, Inc.[5]

In November 2017, Cavium's board of directors agreed to the company's purchase by Marvell Technology Group for $6 billion in cash and stock.[14] The merger was finalized on July 6, 2018.

The cnMIPS microarchitecture implements the MIPS64 instruction set.

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The ThunderX line of SoCs from Cavium were released with up to 48 dual issue, out of order ARMv8 cores.[20][21] These SoCs were targeted at servers in network intensive applications, competing with Intel Xeon products.[22] The ThunderX line is manufactured by Global Foundries at 28 nm and is reported to have a TDP less than 100W.[22]

Sandia National Laboratories' second generation supercomputer in their Vanguard project called Sullivan was based Cavium's ThunderX processors. The first generation was called Hammer, it was based on X-Gene by Applied Micro.[23]

• Comparison of ARMv8-A cores

Cavium announced in 2016 the ThunderX2 line of SoCs, initially as iterative improvement of their ThunderX line.[22][24] The name was later used for the former Vulcan SoC design purchased from Broadcom.[25][26] ThunderX2 has up to 32 custom ARM cores and is manufactured on Global Foundries' 16 nm FinFET process. These and other improvements are reported to offer twice the performance per core of the ThunderX line.

Cray has added "ARM Option" (i.e. CPU blade option, using the ThunderX2) to their XC50 supercomputers, and Cray states that ARM is "a third processor architecture for building next-generation supercomputers", for clients such as the US Department of Energy.[27]

The Cray XC50-series supercomputer for the University of Bristol is called Isambard, named after Isambard Kingdom Brunel. The supercomputer is expected to feature around 160 nodes, each with two 32-core ThunderX2 processors running at 2.1 GHz. Peak theoretical performance of the 10,240 cores and 40,960 threads is 172 teraFLOPS.[28]

The third generation of the Sandia National Laboratories' Vanguard project called Mayer was based on pre-production ThunderX2 and consisted of 47 nodes. The fourth generation also based on ThunderX2 is called Astra and will become operation by November 2018. Each Astra node will feature two 28-core ThunderX2 processors running at 2.0 GHz with 128 GB DDR4. Each rack has 18x Hewlett Packard Enterprise Apollo 70 chassis with 72 compute nodes along with 3 InfiniBand switches. Astra will feature a total of 36 racks. Thus Astra will have 5,184 ThunderX2 processors, 145,152 ThunderX2 cores and 580,608 threads. Astra's peak theoretical performance is 4.644 PFLOPS in Single Precision, and 2.322 PFLOPS in Double Precision and will support 324 TB DDR4.[23] Astra is the first ARM-based Petascale supercomputer to enter the TOP500 list. In November 2018 it is ranked at 204, while as of June 2019 it's ranked at 156 after an upgrade.[29]

On March 2, 2020, Marvell announced OCTEON TX2 and OCTEON Fusion processors feature OCTEON TX2 Microarchitecture.[30]

ThunderX2 Microarchitecture[31][28]:

• ISA: ARMv8.1-A with 128-bit NEON SIMD
• SMT4
• L1-instruction cache: 32 KB with 8-way associativity and Instruction TLB
• L1-data cache: 32 KB with 8-way associativity with 64 entries Load buffer and 36 entries Store Buffer & Forwarding
• Load bandwidth: 2x 16B
• L2 cache: 256 KB with 8-way with associativity and 2048-entry STLB
• L3 cache: 1 MB/core
• Fetch Width: 8 instructions (32-byte window)
• Decode width: 4
• Sustainable instructions/cycle: 4
• Loop buffer: 128 entries
• Instructions in flight: 180-entry ReOrder Buffer (ROB)
• Scheduler/Issue queue: Unified 60 entries
• Issue: 6
• Pipeline: 13–15 stages
• Cavium's Coherent Processor Interconnect 2 (CCPI2) with 600 Gbit/s bandwidth

OCTEON TX2 Microarchitecture[30]:

• ISA: ARMv8.2-A with 128-bit NEON SIMD
• L1-instruction cache: 66 KB
• L1-data cache: 41 KB with 5-way associativity
• Issue: 4

On March 16, 2020, Marvell announced ThunderX3 and their plan for ThunderX4 in 2022.[32]

Microarchitecture details[32]:

• ISA: ARMv8.3-A
• 4 128-bit SIMD units

ThunderX3 SoC details include[32]:

• Up to 96x ThunderX3 cores
• Up to Base Frequency of 2.2 GHz and turbo frequency up to 3 GHz
• Up to 384 threads (SMT4)
• Up to 8-channel DDR4-3200
• Up to 64x PCIe 4.0 lanes
• TSMC N7P
• Up to TDP: 240 W
• Multiprocessing: 1S and 2S configurations with 672 Gbit/s bandwidth using Cavium's Coherent Processor Interconnect 3 (CCPI3)