p–n junction isolation

p–n junction isolation is a method used to electrically isolate electronic components, such as transistors, on an integrated circuit (IC) by surrounding the components with reverse biased p–n junctions.

Introduction

By surrounding a transistor, resistor, capacitor or other component on an IC with semiconductor material which is doped using an opposite species of the substrate dopant, and connecting this surrounding material to a voltage which reverse-biases the p–n junction that forms, it is possible to create a region which forms an electrically isolated "well" around the component.

Operation

Assume that the semiconductor wafer is p-type material. Also assume a ring of n-type material is placed around a transistor, and placed beneath the transistor. If the p-type material within the n-type ring is now connected to the negative terminal of the power supply and the n-type ring is connected to the positive terminal, the 'holes' in the p-type region are pulled away from the p–n junction, causing the width of the nonconducting depletion region to increase. Similarly, because the n-type region is connected to the positive terminal, the electrons will also be pulled away from the junction.

This effectively increases the potential barrier and greatly increases the electrical resistance against the flow of charge carriers. For this reason there will be no (or minimal) electric current across the junction.

At the middle of the junction of the p–n material, a depletion region is created to stand-off the reverse voltage. The width of the depletion region grows larger with higher voltage. The electric field grows as the reverse voltage increases. When the electric field increases beyond a critical level, the junction breaks down and current begins to flow by avalanche breakdown. Therefore, care must be taken that circuit voltages do not exceed the breakdown voltage or electrical isolation ceases.

History

Before the invention of the integrated circuit, discrete diodes and transistors exhibited relatively high reverse-bias junction leakages and low breakdown voltage, caused by the large density of traps at the surface of single crystal silicon. The solution to this problem was the surface passivation process developed by Egyptian engineer Mohamed Atalla at Bell Telephone Laboratories (BTL). He discovered that when a thin layer of silicon dioxide was grown on the surface of silicon where a p–n junction intercepts the surface, the leakage current of the junction was reduced by a factor from 10 to 100. This showed that the oxide reduces and stabilizes many of the interface and oxide traps. Oxide-passivation of silicon surfaces allowed diodes and transistors to be fabricated with significantly improved device characteristics, while the leakage path along the surface of the silicon was also effectively shut off. This became one of the fundamental isolation capabilities necessary for planar technology and integrated circuits.[1] According to Fairchild Semiconductor engineer Chih-Tang Sah, Atalla's surface passivation method was critical to the development of the silicon integrated circuit.[1][2]

Atalla first published his surface passivation method in BTL memos during 1957, before presenting his work at a 1958 Electrochemical Society meeting. This became the basis for Jean Hoerni's planar process, which in turn was the basis for Robert Noyce's monolithic integrated circuit.[3][4]

In an article entitled "Microelectronics", published in Scientific American, September 1977 Volume 23, Number 3, pp. 63–9, Robert Noyce wrote:

"The integrated circuit, as we conceived and developed it at Fairchild Semiconductor in 1959, accomplishes the separation and interconnection of transistors and other circuit elements electrically rather than physically. The separation is accomplished by introducing pn diodes, or rectifiers, which allow current to flow in only one direction. The technique was patented by Kurt Lehovec at the Sprague Electric Company".

Sprague Electric Company engineer Kurt Lehovec filed U.S. Patent 3,029,366 for p–n junction isolation in 1959, and was granted the patent in 1962. He is reported to have said "I never got a dime out of [the patent]."

When Robert Noyce invented the monolithic integrated circuit in 1959, his idea of p–n junction isolation was based on Hoerni's planar process.[5] In 1976, Noyce stated that, in January 1959, he did not know about the work of Lehovec.[6]

See also

References
  1. Wolf, Stanley (March 1992). "A review of IC isolation technologies". Solid State Technology: 63.
  2. Sah, Chih-Tang (October 1988). "Evolution of the MOS transistor-from conception to VLSI" (PDF). Proceedings of the IEEE. 76 (10): 1280–1326 (1290). doi:10.1109/5.16328. ISSN 0018-9219.
  3. Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. pp. 120& 321-323. ISBN 9783540342588.
  4. Bassett, Ross Knox (2007). To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology. Johns Hopkins University Press. p. 46. ISBN 9780801886393.
  5. Brock, D.; Lécuyer, C. (2010). Lécuyer, C. (ed.). Makers of the Microchip: A Documentary History of Fairchild Semiconductor. MIT Press. p. 158. ISBN 9780262014243.
  6. "Interview with Robert Noyce, 1975–1976". IEEE. Archived from the original on 2012-09-19. Retrieved 2012-04-22.
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