Tensilica

Xtensa configurable cores

An Xtensa processor can be customized into anything from a small, low-power cache-less microcontroller to a high-performance 16-way SIMD processor, 3-issue VLIW DSP core, or a 1 TMAC/sec neural network processor. All Cadence standard DSPs are based on the Xtensa architecture.

IP processor vendors such as Tensilica typically offer their licensees the choice between many of the IP core's implementation details: cache size, processor bus width, data and instruction RAMs, memory management and interrupt control. However, Cadence's Xtensa architecture offers a key differentiating feature, a user-customizable instruction set.

Using the supplied customization tools, customers can extend the Xtensa base instruction set by adding new user-defined instructions. Extensions can include SIMD instructions, new register files, and additional data transfer interfaces for multiprocessor communication. After the final processor configuration is made and submitted, the Tensilica processor generator service builds the configured Xtensa IP core, processor design kit, and software development kit. This process is highly automated so designers can quickly experiment with different instruction additions, testing the performance improvements and power trade-offs of the various alternatives.

The processor kit contains items necessary to integrate the configured IP into the customer's chip design environment: the core's hardware description (in synthesizeable RTL or physical post-layout form), timing & I/O constraints, requirements for technology-specific RAMs/caches/FIFOs. The software kit is built on the Eclipse-based integrated development environment, and uses a GNU Compiler Collection-derived tool-chain: C/C++ compiler, assembler, linker, debugger. An instruction set simulator enables customers to begin application development before actual hardware is available.

HiFi Audio and Voice DSP IP

Simplified block diagrams of HiFi Audio Engine and Xtensa LX.

• HiFi Mini Audio DSP — A small, low power DSP core for voice triggering and voice recognition
• HiFi 2 Audio DSP — DSP core for low power MP3 audio processing
• HiFi EP Audio DSP — A superset of HiFi 2 with optimizations for DTS Master Audio, voice pre- and post-processing, and cache management
• HiFi 3 Audio DSP — 32-bit DSP for audio enhancement algorithms, wideband voice codecs, and multi-channel audio
• HiFi 3z Audio DSP — For lower-powered audio, wideband voice codecs, and neural-network-based speech recognition.
• HiFi 4 DSP - Higher performance DSP for applications such as multi-channel object-based audio standards.

Vision DSPs

• Vision P5 DSP, which offers 4–100x the performance relative to traditional mobile CPU+GPU systems at a fraction of the power/energy^[4].
• Vision P6 DSP, with 4X the peak performance of the Vision P5 DSP for demanding image and computer vision applications^[5].
• Vision C5 DSP, with 1 TMAC/sec computational capacity to run all neural network computational tasks without the need for additional hardwired accelerators^[6].

Adoption

AMD TrueAudio, found e.g. in the PlayStation 4, in "Kaveri" desktop APUs and in a very few of AMD's graphics cards, is based on the Cadence Tensilica HiFi EP Audio DSP.^[7]

Microsoft HoloLens uses special custom-designed TSMC-fabricated 28nm coprocessor that has 24 Tensilica DSP cores. It has around 65 million logic gates, 8 MB of SRAM, and an additional layer of 1 GB of low-power DDR3 RAM.^[8]

Espressif ESP8266 Wi-Fi IoT SoC integrates the Tensilica Diamond Standard 106Micro 32-bit controller processor core, which Espressif calls L106.

Spreadtrum licensed the HiFi DSP for smartphones^[9]

VIA Technologies uses a HiFi DSP in an SoC for set top box, tablets, and mobile devices^[10].

Realtek standardized on the HiFi Audio DSP for mobile and PC products^[11].

Over 80 top-tier semiconductor companies and system OEM customers use HiFi audio DSPs in their chip designs.