PIC instruction listings

The PIC instruction set refers to the set of instructions that a Microchip Technology PIC or dsPIC microcontroller supports. The instructions are usually programmed into the Flash memory of the processor, and automatically executed by the microcontroller on startup.

PICmicro chips have a Harvard architecture, and instruction words are unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits.

In the instruction set tables that follow, register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". The "d" bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.


Architecture

Memory operands are also referred to as "registers". Most are simply general-purpose storage (RAM), while some locations are reserved for special function registers. Except for a single accumulator (called W), almost all other registers are memory-mapped, even registers like the program counter and ALU status register. (The other exceptions, which are not memory-mapped, are the return address stack, and the tri-state registers used to configure the GPIO pins.)

The instruction set does not contain conditional branch instructions. Instead, it contains conditional skip instructions which cause the following instruction to be ignored. A conditional skip followed by an unconditional branch performs a conditional branch. The skip instructions test any bit of any register. The ALU status register is one possibility.

Memory operands are specified by absolute address; the location is fixed at compile time. To provide indirect addressing, a pair of special function registers are provided:

  • The file select register (FSR) is written with the address of the desired memory operand, after which
  • The indirect file register (INDF) becomes an alias for the operand pointed to by the FSR.

This mechanism also allows up to 256 bytes of memory to be addressed, even when the instruction set only allows 5- or 7-bit memory operands. Models with more registers (special function registers plus RAM) than fit into the instruction provide multiple banks of memory, and use one of two mechanisms for accessing them:

  1. Most baseline core devices, and some mid-range core devices, use the high-order bits of the file select register to select the current register bank.
  2. More recent models have a separate bank select register, and a MOVLB instruction to set it.

PIC processors with more than 256 words of program use paged memory. The internal program counter and return stack are as wide as necessary to address all memory, but only the low 8 bits are visible to software in the PCL ("PC low") register. There is an additional PCLATH ("PC latch high") register which is only modified by software. Any operation which does not specify the full destination address (such as a 9-bit GOTO or an 8-bit write to the PC register) fills in the additional high bits from the corresponding part of PCLATH. (Some PIC18 processors extend this beyond 16 bits with a PCLATU register to supply bits 16–23.)

Baseline core devices (12 bit)

12-bit PIC instruction set
1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
0000000opcodeMiscellaneous instructions
000000000000NOPNo operation (MOVW 0,W)
000000000010OPTIONCopy W to OPTION register
000000000011SLEEPGo into standby mode
000000000100CLRWDTRestart watchdog timer
0000000001fTRIS fCopy W to tri-state register (f = 1, 2 or 3)
000000010kMOVLB k*Set bank select register to k
000000011110RETURN†Return from subroutine, W unmodified
000000011111RETFIE†Return from interrupt; return & enable interrupts
00opcodedregisterALU operations: dest ← OP(f,W)
0000001fMOVWF fdest ← W
000001dfCLR f,dZdest ← 0, usually written CLRW or CLRF f
000010dfSUBWF f,dCZdest ← f−W (dest ← f+~W+1)
000011dfDECF f,dZdest ← f−1
000100dfIORWF f,dZdest ← f | W, logical inclusive or
000101dfANDWF f,dZdest ← f & W, logical and
000110dfXORWF f,dZdest ← f ^ W, logical exclusive or
000111dfADDWF f,dCZdest ← f+W
001000dfMOVF f,dZdest ← f
001001dfCOMF f,dZdest ← ~f, bitwise complement
001010dfINCF f,dZdest ← f+1
001011dfDECFSZ f,ddest ← f−1, then skip if zero
001100dfRRF f,dCdest ← CARRY<<7 | f>>1, rotate right through carry
001101dfRLF f,dCdest ← F<<1 | CARRY, rotate left through carry
001110dfSWAPF f,ddest ← f<<4 | f>>4, swap nibbles
001111dfINCFSZ f,ddest ← f+1, then skip if zero
01opcbitregisterBit operations
0100bitfBCF f,bClear bit b of f
0101bitfBSF f,bSet bit b of f
0110bitfBTFSC f,bSkip if bit b of f is clear
0111bitfBTFSS f,bSkip if bit b of f is set
10opckControl transfers
1000kRETLW kSet W ← k, then return from subroutine
1001kCALL kCall subroutine, 8-bit address k
101kGOTO kJump to 9-bit address k[1]
11opc8-bit immediateOperations with W and 8-bit literal: W ← OP(k,W)
1100kMOVLW kW ← k
1101kIORLW kZW ← k | W, bitwise logical or
1110kANDLW kZW ← k & W, bitwise and
1111kXORLW kZW ← k ^ W, bitwise exclusive or
1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description

*: Extended instruction, not available on most 12-bit PICs. Of the models with extended RAM, most (e.g. 16C5x, 16F5x) extend the register address space using the high-order bits of the FSR. A few (e.g. PIC12F529T39A) have a separate bank select register which can be set with this instruction.
†: Extended instruction, only available on "enhanced baseline" PICs. Only the very few models (16F527, 16F570, MCV20A) with interrupt support (and a 4-level stack) include these instructions. All such models also include MOVLB.

ELAN Microelectronics clones (13 bit)

ELAN Microelectronics Corp. make a series of PICmicro-like microcontrollers with a 13-bit instruction word.[2] The instructions are mostly compatible with the mid-range 14-bit instruction set, but limited to a 6-bit register address (16 special-purpose registers and 48 bytes of RAM) and a 10-bit (1024 word) program space.

The 10-bit program counter is accessible as R2. Reads access only the low bits, and writes clear the high bits. An exception is the TBL instruction, which modifies the low byte while preserving bits 8 and 9.

The 7 accumulator-immediate instructions are renumbered relative to the 14-bit PICmicro, to fit into 3 opcode bits rather than 4, but they are all there, as well as an additional software interrupt instruction.

There are a few additional miscellaneous instructions, and there are some changes to the terminology (the PICmicro OPTION register is called the CONTrol register; the PICmicro TRIS registers 1–3 are called I/O control registers 5–7), but the equivalents are obvious.

13-bit EM78 instruction set[3]
1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
0000000opcodeMiscellaneous instructions
0000000000000NOP*No operation (MOVW 0,W)
0000000000001DAA†CDecimal Adjust after Addition
0000000000010CONTW*Write CONT register (CONT ← W)
0000000000011SLEEP*Go into standby mode (WDT ← 0, stop clock)
0000000000100CLRWDT*Restart watchdog timer (WDT ← 0)
000000000fIOW f*Copy W to I/O control register (f = 5–7, 11–15)
0000000010000ENI†Enable interrupts
0000000010001DISI†Disable interrupts
0000000010010RETReturn from subroutine, W unmodified
0000000010011RETIReturn from interrupt; return & enable interrupts
0000000010100CONTR†Read CONT register (W ← CONT)
000000001fIOR f†Copy I/O control register to W (f = 5–7, 11–15)
0000000100000TBL†CZPCL += W, preserve PC bits 8 & 9
00opcodedregisterALU operations same as 12- and 14-bit PIC
01opcbitregisterBit operations same as 12- and 14-bit PIC
10ckControl transfers same as 14-bit PIC
11opcode8-bit immediateOperations with W and 8-bit literal: W ← OP(k,W)
110opkMOV/IOR/AND/XOR, same as 12-bit PIC
11100kRETLW kW ← k, then return from subroutine
11101kSUBLW kCZW ← k−W (W ← k+~W+1)
11110kINT k†Push PC, PC ← k (software interrupt, usually k=1)
11111kADDLW kCZW ← k+W
1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description

*: Same opcode as 12-bit PIC
†: Instruction unique to EM78 instruction set with no PIC equivalent

Some models support multiple ROM or RAM banks, in a manner similar to other PIC microcontrollers.

Mid-range core devices (14 bit)

These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the 2 additional opcode bits allow 128 registers and 2048 words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.

14-bit PIC instruction set
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
0000000opcodeMiscellaneous instructions
00000000000000NOPNo operation (MOVW 0,W)
00000000001000RETURNReturn from subroutine, W unmodified
00000000001001RETFIEReturn from interrupt
00000001100010OPTIONCopy W to OPTION register (deprecated)
00000001100011SLEEPGo into standby mode
00000001100100CLRWDTRestart watchdog timer
000000011001fTRIS fCopy W to tri-state register (f = 1, 2 or 3) (deprecated)
00opcodedregisterALU operations: dest ← OP(f,W)
0000001fMOVWF ff ← W
000001dfCLR f,dZdest ← 0, usually written CLRW or CLRF f
000010dfSUBWF f,dCZdest ← f−W (dest ← f+~W+1)
000011dfDECF f,dZdest ← f−1
000100dfIORWF f,dZdest ← f | W, logical inclusive or
000101dfANDWF f,dZdest ← f & W, logical and
000110dfXORWF f,dZdest ← f ^ W, logical exclusive or
000111dfADDWF f,dCZdest ← f+W
001000dfMOVF f,dZdest ← f
001001dfCOMF f,dZdest ← ~f, bitwise complement
001010dfINCF f,dZdest ← f+1
001011dfDECFSZ f,ddest ← f−1, then skip if zero
001100dfRRF f,dCdest ← CARRY<<7 | f>>1, rotate right through carry
001101dfRLF f,dCdest ← f<<1 | CARRY, rotate left through carry
001110dfSWAPF f,ddest ← f<<4 | f>>4, swap nibbles
001111dfINCFSZ f,ddest ← f+1, then skip if zero
01opcbitregisterBit operations
0100bitfBCF f,bClear bit b of f
0101bitfBSF f,bSet bit b of f
0110bitfBTFSC f,bSkip if bit b of f is clear
0111bitfBTFSS f,bSkip if bit b of f is set
10ckControl transfers
100kCALL kCall subroutine
101kGOTO kJump to address k
11opcode8-bit immediateOperations with W and 8-bit literal: W ← OP(k,W)
1100xxkMOVLW kW ← k
1101xxkRETLW kW ← k, then return from subroutine
111000kIORLW kZW ← k | W, bitwise logical or
111001kANDLW kZW ← k & W, bitwise and
111010kXORLW kZW ← k ^ W, bitwise exclusive or
111011k(reserved)
11110xkSUBLW kCZW ← k−W (dest ← k+~W+1)
11111xkADDLW kCZW ← k+W
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description

Enhanced mid-range core devices (14 bit)

Enhanced mid-range core devices introduce a deeper hardware stack, additional reset methods, 14 additional instructions and ‘C’ programming language optimizations [4]. In particular. there are two INDF registers (INDF0 and INDF1), and two corresponding FSR register pairs (FSRnL and FSRnH). Special instructions use FSRn registers like address registers, with a variety of addressing modes.

14-bit enhanced PIC additional instructions
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description
0000000opcodeMiscellaneous instructions
00000000000001RESETSoftware reset
00000000001010CALLWPush PC, then jump to PCLATH:W
00000000001011BRWPC ← PC + W, relative jump using W
00000000010n00MOVIW ++FSRnZIncrement FSRn, then W ← INDFn
00000000010n01MOVIW −−FSRnZDecrement FSRn, then W ← INDFn
00000000010n10MOVIW FSRn++ZW ← INDFn, then increment FSRn
00000000010n11MOVIW FSRn−−ZW ← INDFn, then decrement FSRn
00000000011nmMOVWI using FSRnINDFn ← W, same modes as MOVIW
000000001kMOVLB kBSR ← k, move literal to bank select register
11opcodedregisterALU operations: dest ← OP(f,W)
110101dfLSLF f,dCZdest ← f << 1, logical shift left
110110dfLSRF f,dCZdest ← f >> 1, logical shift right
110111dfASRF f,dCZdest ← f >> 1, arithmetic shift right
111011dfSUBWFB f,dCZdest ← f + ~W + C, subtract with carry
111101dfADDWFC f,dCZdest ← f + W + C, add with carry
11opcodekOperations with literal k
1100010nkADDFSR FSRn,kFSRn ← FSRn + k, add 6-bit signed offset
1100011kMOVLP kPCLATH ← k, move 7-bit literal to PC latch high
11001kBRA kPC ← PC + k, branch relative using 9-bit signed offset
1111110nkMOVIW k[FSRn]ZW ← [FSRn+k], 6-bit signed offset
1111111nkMOVWI k[FSRn][FSRn+k] ← W, 6-bit signed offset
1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		Description

PIC18 high end core devices (16 bit)

In 2000, Microchip introduced the PIC18 architecture. Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language.[5]

The PIC18 has a 12-bit RAM address space, divided into 16 pages of 256 bytes. The 8-bit f field determines the address in combination with the a bit and the 4-bit bank select register (BSR). If a=0, the BSR is ignored and the f field is sign-extended to the range 0x000–0x07F (global RAM) or 0xF80–0xFFF (special function registers). If a=1, the f field is extended with the BSR to generate the 12-bit address.

The PIC18 extends the FSR/INDF mechanism used in previous PICmicro processors for indirect addressing in two ways. First, it provides three file select registers. The FSRn registers are 12 bits long (each split into two 8-bit portions FSR0L through FSR2H), and access to the corresponding INDFn register (INDF0 through INDF2) acts as an alias for the addressed byte.

Second, there are addressing modes. For each of the three, there is not just one INDFn register, but five, and the one used determines the addressing mode:

  • INDFn: Access the byte at location FSRn
  • POSTDECn: Access the byte at FSRn, then decrement FSRn
  • POSTINCn: Access the byte at FSRn, then increment FSRn
  • PREINCn: Increment FSRn, then access the byte at the incremented FSRn
  • PLUSWn: Access the byte at FSRn + W (indexed addressing)

There are also instructions to directly load an FSR pair with a 12-bit address, and a MOVFF instruction that moves a byte between two 12-bit addresses.

PIC18 16-bit instruction set[6]
1
5		1
4		1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		N
?		Description
00000000opcodeMiscellaneous instructions
0000000000000000NOPNo operation
0000000000000011SLEEPGo into standby mode
0000000000000100CLRWDTRestart watchdog timer
0000000000000101PUSHPush PC on top of stack
0000000000000110POPPop (and discard) top of stack
0000000000000111DAWCDecimal adjust W
0000000000001000TBLRD∗Table read: TABLAT ← mem[TBLPTR]
0000000000001001TBLRD∗+Table read with postincrement
0000000000001010TBLRD∗−Table read with postdecrement
0000000000001011TBLRD+∗Table read with pre-increment
00000000000011modTBLWRTable write, same modes as TBLRD
000000000001000sRETFIE [, FAST]Return from interrupt
000000000001001sRETURN [, FAST]Return from subroutine
0000000000010100CALLW*Push PC, jump to PCLATU:PCLATH:W
0000000011111111RESET000Software reset
00000001—0—kMOVLBMove literal k to bank select register
00001opcodeliteralLiteral operations: W ← OP(k,W)
00001000kSUBLW kW ← k − W
00001001kIORLW kW ← k | W, logical inclusive or
00001010kXORLW kW ← k ^ W, exclusive or
00001011kANDLW kW ← k & W, logical and
00001100kRETLW kRETURN W ← k
00001101kMULLW kW ← k × W
00001110kMOVLW kW ← k
00001111kADDLW kW ← k + W
0opcodedaregisterALU operations: dest ← OP(f,W)
0000001afMULWF f,aPRODH:PRODL ← W × f (unsigned)
000001dafDECF f,d,aCZNdest ← f − 1
000100dafIORWF f,d,aZNdest ← f | W, logical inclusive or
000101dafANDWF f,d,aZNdest ← f & W, logical and
000110dafXORWF f,d,aZNdest ← f ^ W, exclusive or
000111dafCOMF f,d,aZNdest ← ~f, bitwise complement
001000dafADDWFC f,d,aCZNdest ← f + W + C
001001dafADDWF f,d,aCZNdest ← f + W
001010dafINCF f,d,aCZNdest ← f + 1
001011dafDECFSZ f,d,adest ← f − 1, skip if 0
001100dafRRCF f,d,aCZNdest ← f>>1 | C<<7, rotate right through carry
001101dafRLCF f,d,aCZNdest ← f<<1 | C, rotate left through carry
001110dafSWAPF f,d,adest ← f<<4 | f>>4, swap nibbles
001111dafINCFSZ f,d,adest ← f + 1, skip if 0
010000dafRRNCF f,d,aZNdest ← f>>1 | f<<7, rotate right (no carry)
010001dafRLNCF f,d,aZNdest ← f<<1 | f>>7, rotate left (no carry)
010010dafINFSNZ f,d,adest ← f + 1, skip if not 0
010011dafDCFSNZ f,d,adest ← f − 1, skip if not 0
010100dafMOVF f,d,aZNdest ← f
010101dafSUBFWB f,d,aCZNdest ← W + ~f + C (dest ← W − f − C̅)
010110dafSUBWFB f,d,aCZNdest ← f + ~W + C (dest ← f − W − C̅)
010111dafSUBWF f,d,aCZNdest ← f − W (dest ← f + ~W + 1)
0110opcodearegisterALU operations, do not write to W
0110000afCPFSLT f,askip if f < W (unsigned)
0110001afCPFSEQ f,askip if f == W
0110010afCPFSGT f,askip if f > W (unsigned)
0110011afTSTFSZ f,askip if f == 0
0110100afSETF f,af ← 0xFF
0110101afCLRF f,a1f ← 0, PSR.Z ← 1
0110110afNEGF f,aCZNf ← −f
0110111afMOVWF f,af ← W
0111bitafBTG f,b,aToggle bit b of f
10opcbitaregisterBit operations
1000bitafBSF f,b,aSet bit b of f
1001bitafBCF f,b,aClear bit b of f
1010bitafBTFSS f,b,aSkip if bit b of f is set
1011bitafBTFSC f,b,aSkip if bit b of f is clear
110opcaddressLarge-address operations
1100sourceMOVFF s,dMove absolute
1111destination
11010nBRA nBranch to PC + 2n
11011nRCALL nSubroutine call to PC + 2n
11100condnConditional branch (to PC+2n)
11100000nBZ nBranch if PSR.Z is set
11100001nBNZ nBranch if PSR.Z is clear
11100010nBC nBranch if PSR.C is set
11100011nBNC nBranch if PSR.C is clear
11100100nBOV nBranch if PSR.V is set
11100101nBNOV nBranch if PSR.V is clear
11100110nBN nBranch if PSR.N is set
11100111nBNN nBranch if PSR.N is clear
111010opckExtensions for using FSR2 as software stack pointer*
11101000nkADDFSR n,k*FSRn += k
1110100011kADDULNK k*FSR2 += k, pop PC
11101001nkSUBFSR n,k*FSRn −= k
1110100111kADDULNK k*FSR2 −= k, pop PC
11101010kPUSHL k*[FSR2] ← k, decrement FSR2
111010110sMOVSF src,f *f ← FSR2[s]
1111f
111010110sMOVSD src,dst*FSR2[d] ← FSR2[s]
1111—0—d
111011opck2-word instructions
1110110sk (lsbits)CALL k[, FAST]Call subroutine (20-bit address)
1111k (msbits)
1110111000fk (msb)LFSR f,kMove 12-bit literal to FSRf
11110000k (lsbits)
11101111k (lsbits)GOTO kAbsolute jump, PC ← k (20-bit address)
1111k (msbits)
1111kNo operation, second word of 2-word instructions
1
5		1
4		1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		N
?		Description

*: These extended instructions are only available on some models, and then only if the XINST configuration bit is set.

PIC24 and dsPIC 16-bit microcontrollers

In 2001, Microchip introduced the dsPIC series of chips,[7] which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition.

Instructions come in two main varieties. One is like the classic one-operand PIC instructions, with an operation between W0 and a value in a specified f register (i.e. the first 8K of RAM), and a destination select bit selecting which is updated with the result. The W registers are memory-mapped, so the f operand may specify a W register.

The other form, new to the PIC24, specifies three W register operands, two of which allow a 3-bit addressing mode specification:

PIC24 addressing modes
source operanddestination operandDescription
pppRegSyntaxqqqRegSyntax
000ssssWs000ddddWdRegister direct
001ssss[Ws]001dddd[Wd]Indirect
010ssss[Ws−−]010dddd[Wd−−]Indirect with postdecrement
011ssss[Ws++]011dddd[Wd++]Indirect with postincrement
100ssss[−−Ws]100dddd[−−Wd]Indirect with predecrement
101ssss[++Ws]101dddd[++Wd]Indirect with preincrement
11kkkkk#u5(Unused, illegal)5-bit unsigned immediate
11xssss[Ws+Ww]11xdddd[Wd+Ww]Indirect with register offset

The register offset addressing mode is only available for the MOV src,dst instruction, where the Ww register may be used as a register offset for the source, destination, or both. All other instructions use this encoding for an unsigned 5-bit immediate source instead.

For the operands to TBLRD and TBLWT which access program memory, only the indirect modes are allowed, and refer to addresses in code memory.

A few instructions are 2 words long. The second word is a NOP, which includes up to 16 bits of additional immediate operand.

PIC24 24-bit instruction set[8]
2
3		2
2		2
1		2
0		1
9		1
8		1
7		1
6		1
5		1
4		1
3		1
2		1
1		1
0
9
8
7
6
5
4
3
2
1
0		MnemonicC
?		Z
?		N
?		Description
0000opcodeoffsetControl transfers
00000000—NOPNo operation
00000000—0—n<22:16>CALL/GOTO addr23(second word)
00000000nDO #k,addr(second word)
000000010opc—0—aComputed control transfer (to 16-bit Wa)
00000001000—0—aCALL RaPush PC, jump to Wa
00000001001—0—aRCALL RaPush PC, jump to PC+2×Wa
00000001010—0—aGOTO RaJump to Wa
00000001011—0—aBRA RaJump to PC+2×Wa
00000010n<15:1>0CALL addr23Push PC, jump to absolute address
—0——0—n<22:16>
00000011—(Reserved)
00000100n0GOTO addr23Jump to absolute address
—0——0—n<22:16>
000001010BkdRETLW[.B] #k,WdWd = k, pop PC
0000011000—0—RETURNpop PC
0000011001—0—RETFIECZNpop SR, PC
00000111nRCALL addressPush PC, PC += 2×s16
0000100000kDO #k,addrZero-overhead loop: k+1 is repeat count, PC+2×n last instruction
—0—n
0000100000kREPEAT #kRepeat next instruction k+1 times
00001000nRCALL addressPush PC, PC += 2×s16
0000101—(Reserved)
0000110anBRA Oa, addrIf accumulator a overflowed/saturated, PC += 2×simm16
0000111anBRA Sa, addr
0opcodewBqdpsReverse subtract: dest ← source − Ww
00010wBqdpsSUBR[.B] Ww,src,dstCZNdst ← src − Ww = src + ~Ww + 1)
00011wBqdpsSUBBR[.B] Ww,src,dstCZNdst ← src − Ww − C̅ = src + ~Ww + C
0010kdMOV #k,WdWd ← #imm16
0011condnConditional branch to PC+2×n
00110000nBRA OV,addr...if PSR.V is set
00110001nBRA C,addr...if PSR.C is set
00110010nBRA Z,addr...if PSR.Z is set
00110011nBRA N,addr...if PSR.N is set
00110100nBRA LE,addr...if PSR.Z, or PSR.N ≠ PSR.V
00110101nBRA LT,addr...if PSR.N ≠ PSR.V
00110110nBRA LEU,addr...if PSR.Z is set, or PSR.C is clear
00110111nBRA addr...unconditionally
00111000nBRA NOV,addr...if PSR.V is clear
00111001nBRA NC,addr...if PSR.C is clear
00111010nBRA NZ,addr...if PSR.Z is clear
00111011nBRA NN,addr...if PSR.N is clear
00111100nBRA GT,addr...if PSR.Z is clear, and PSR.N = PSR.V
00111101nBRA GE,addr...if PSR.N = PSR.V
00111110nBRA GTU,addr...if PSR.Z is clear, and PSR.C is set
00111111n(Reserved)
0opcodewBqdpsALU operations: dest ← OP(Ww,source)
01000wBqdpsADD[.B] Ww,src,dstCZNdst ← Ww + src
01001wBqdpsADDC[.B] Ww,src,dstCZNdst ← Ww + src + C
01010wBqdpsSUB[.B] Ww,src,dstCZNdst ← Ww − src
01011wBqdpsSUBB[.B] Ww,src,dstCZNdst ← Ww − ~src − C̅ = Ww + ~src + C
01100wBqdpsAND[.B] Ww,src,dstZNdst ← Ww & src
01101wBqdpsXOR[.B] Ww,src,dstZNdst ← Ww ^ src
01110wBqdpsIOR[.B] Ww,src,dstZNdst ← Ww | src
01111wBqdpsMOV[.B] src,dstZNdst ← src (offset mode allowed)
10000fdMOV f,WdWd ← f
10001fsMOV Ws,ff ← Ws
10010kBkdksMOV[.B] [Ws+s10],WdLoad with 10-bit offset
10011kBkdksMOV[.B] Ws,[Wd+s10]Store with 10-bit offset
10100opcodebZB—0—psBit operations on source
10100000b0B—0—psBSET[.B] #b,srcSet bit b of src
10100001b0B—0—psBCLR[.B] #b,srcClear bit b of src
10100010b0B—0—psBTG[.B] #b,srcToggle bit b of src
10100011b00—0—psBTST.C #b,srcCSet PSR.C = bit b of src
10100011b10—0—psBTST.Z #b,srcZSet PSR.Z = bit b of src
10100100bZ0—0—psBTSTS.z #b,srcC/ZTest bit b of src (into C or Z), then set
10100101Zw0—0—psBTST.z Ww,srcC/ZTest bit Ww of src
10100110b00—0—psBTSS #b,srcTest bit, skip if set
10100111b00—0—psBTS #b,srcTest bit, skip if clear
10101opcodebfBit operations on f
10101000bfbBSET[.B] f,#bSet bit b of f
10101001bfBCLR.B f,#bClear bit b of f
10101010bfBTG.B f,#bToggle bit b of f
10101011bfBTST.B f,#bZTest bit b of f
10101100bfBTSTS.B f,#bZTest bit b of f, then set
10101101Zw0—0—psBSW.z src,WwCopy PSW.C or PSW.Z to bit Ww of src
10101110bfBTSS f,#bTest bit, skip if set
10101111bfBTSC f,#bTest bit, skip if clear
101100opcodeBkdRegister-immediate operations: Wd ← OP(Wd,k)
101100000BkdADD[.B] #u10,WdCZNWd ← Wd + k
101100001BkdADC[.B] #u10,WdCZNWd ← Wd + k + C
101100010BkdSUB[.B] #u10,WdCZNWd ← Wd − k
101100011BkdSUBB[.B] #u10,WdCZNWd ← Wd − k − C̅
101100100BkdAND[.B] #u10,WdZNWd ← Wd & k
101100101BkdXOR[.B] #u10,WdZNWd ← Wd ^ k
101100110BkdIOR[.B] #u10,WdZNWd ← Wd | k
101100111BkdMOV[.B] #u10,WdWd ← k
101101opcodeBDfALU operations: dest ← OP(f,W0)
101101000BDfADD[.B] f[,WREG]CZNdest ← f + W0
101101001BDfADC[.B] f[,WREG]CZNdest ← f + W0 + C
101101010BDfSUB[.B] f[,WREG]CZNdest ← f − W0
101101011BDfSUBB[.B] f[,WREG]CZNdest ← f − W0 + C̅
101101100BDfAND[.B] f[,WREG]ZNdest ← f & W0
101101101BDfXOR[.B] f[,WREG]ZNdest ← f ^ W0
101101110BDfIOR[.B] f[,WREG]ZNdest ← f | W0
101101111B1fMOV[.B] WREG,ff ← W0
1011100opcwd0ps16×16→32 multiplication
101110000wd0psMUL.UU Ww,src,WdWd+1:Wd ← Ww × src (unsigned)
101110001wd0psMUL.US Ww,src,WdWd+1:Wd ← Ww × src (src signed)
101110010wd0psMUL.SU Ww,src,WdWd+1:Wd ← Ww × src (Ww signed)
101110011wd0psMUL.SS Ww,src,WdWd+1:Wd ← Ww × src (signed)
1011101opcBqdpsProgram memory access (indirect modes only)
101110100BqdpsTBLRDL[.B] src,dstdst ← ROM[TBLPAG:src] (bits 15:0)
101110101BqdpsTBLRDH[.B] src,dstdst ← ROM[TBLPAG:src] (bits 23:16)
101110110BqdpsTBLWTL[.B] src,dstROM[TBLPAG:dst] ← src (bits 15:0)
101110111BqdpsTBLWTH[.B] src,dstROM[TBLPAG:dst] ← src (bits 23:16)
101111000B0fMUL[.B] fW3:W2 ← f × W0 (unsigned)
101111000B1—(Reserved)
101111001—(Reserved)
10111101—(Reserved)
1011111000—0—d0psMOV.D src,WdLoad register pair
1011111010qd—0—s0MOV.D Ws,dstStore register pair
10111111—(Reserved)
11000mASxyijaDSP MAC (dsPIC only)
11001Other DSP instructions (dsPIC only)
1100111100—0—dpsFF1R src,WdCFind first one from right (lsb)
1100111110—0—dpsFF1L src,WdCFind first one from left (msb)
110100opcodeBqdpsShift/rotate general operand
110100000BqdpsSL[.B] src,dstCZNdst ← src << 1, shift left (into carry)
110100010BqdpsLSR[.B] src,dstCZNdst ← src >> 1, logical shift right
110100011BqdpsASR[.B] src,dstCZNdst ← src >> 1, arithmetic shift right
110100100BqdpsRLNC[.B] src,dstZNdst ← src <<< 1, rotate left (no carry)
110100101BqdpsRLC[.B] src,dstCZNC:dst ← src:C << 1, rotate left through carry
110100110BqdpsRRNC[.B] src,dstZNdst ← src >>> 1, rotate right (no carry)
110100111BqdpsRRC[.B] src,dstCZNdst:C ← C:src >> 1, rotate right through carry
110101opcodeBDfShift/rotate f
110101000BDfSL[.B] f[,WREG]CZNdest ← f << 1, shift left (into carry)
110101010BDfLSR[.B] f[,WREG]CZNdest ← f >> 1, logical shift right
110101011BDfASR[.B] f[,WREG]CZNdest ← f >> 1, arithmetic shift right
110101100BDfRLNC[.B] f[,WREG]ZNdest ← f <<< 1, rotate left (no carry)
110101101BDfRLC[.B] f[,WREG]CZNC:dest ← f:C << 1, rotate left through carry
110101110BDfRRNC[.B] f[,WREG]ZNdest ← f >>> 1, rotate right (no carry)
110101111BDfRRC[.B] f[,WREG]CZNdest:C ← C:f >> 1, rotate right through carry
11011000UtdD00sDivide step (prefix with REPEAT #17)
110110000—0—d000sDIV.S Wd,WsCZNW0 ← Wd/Ws, W1 ← remainder
110110000td100sDIV.SD Wd,WsCZNW0 ← Wt:Wd/Ws, W1 ← remainder
110110001—0—d000sDIV.U Wd,WsCZNW0 ← Wd/Ws, W1 ← remainder
110110001td100sDIV.UD Wd,WsCZNW0 ← Wt:Wd/Ws, W1 ← remainder
110110010t—0—000sDIVF Wt,WsCZNW0 ← Wt:0/Ws, W1 ← remainder
110110011—(Reserved)
1101101—(Reserved)
110111opcodewdi00sShift/rotate multiple
110111000wd000sSL Ww,Ws,WdZNWd ← Ww << Ws
110111000wd100kSL Wv,#u4,WdZNWd ← Ww << k
110111100wd000sLSR Ww,Ws,WdZNWd ← Ww >> Ws, logical shift right
110111100wd100kLSR Wv,#u4,WdZNWd ← Ww >> k, logical shift right
110111101wd000sASR Ww,Ws,WdZNWd ← Ww >> Ws, arithmetic shift right
110111101wd100kASR Wv,#u4,WdZNWd ← Ww >> k, arithmetic shift right
110111110—0—dpsFBCL src,WdCFind permissible arithmetic normalization shift
111000000—0—B000psCP0[.B] srcCZNCompare with zero, src − 0
111000010wB000psCP[.B] Ww,srcCZNCompare, Ww − src (Ww + ~src + 1)
111000011wB000psCPB[.B] Ww,srcCZNCompare with borrow, Ww − src − C̅ (Ww + ~src + C)
111000100B0fCP0[.B] fCZNCompare with zero, f − 0
111000110B0fCP[.B] fCZNCompare, f − W0
111000111B0fCPB[.B] fCZNCompare with borrow, f − W0 − C̅ (f + ~W0 + C)
1110010—(Reserved)
1110011opcwB—0—sCompare and skip
111001100wB—0—sCPSGT[.B] Ww,Ws...if Ww > Ws, signed
111001101wB—0—sCPSLT[.B] Ww,Ws...if Ww < Ws, signed
111001110wB—0—sCPSNE[.B] Ww,Ws...if Ww ≠ Ws
111001111wB—0—sCPSNE[.B] Ww,Ws...if Ww = Ws
111010000BqdpsINC[.B] src,dstCZNdst ← src+1
111010001BqdpsINC2[.B] src,dstCZNdst ← src+2
111010010BqdpsDEC[.B] src,dstCZNdst ← src−1
111010011BqdpsDEC2[.B] src,dstCZNdst ← src−2
111010100BqdpsNEG[.B] src,dstCZNdst ← ~src+1
111010101BqdpsCOM[.B] src,dstZNdst ← ~src
111010110Bqd—0—CLR[.B] dstdst ← 0
111010111Bqd—0—SETM[.B] dstdst ← ~0
111011000BDfINC[.B] f[,WREG]CZNdest ← f+1
111011001BDfINC2[.B] f[,WREG]CZNdest ← f+2
111011010BDfDEC[.B] f[,WREG]CZNdest ← f−1
111011011BDfDEC[.B] f[,WREG]CZNdest ← f−2
111011100BDfNEG[.B] f[,WREG]CZNdest ← ~f+1
111011101BDfCOM[.B] f[,WREG]ZNdest ← ~f
111011110BDfCLR[.B] f[,WREG]dest ← 0
111011111BDfSETM[.B] f[,WREG]dest ← ~0
111100mA1xyijopcDSP MPY/MAC/ED/EDAC (dsPIC only)
111101—(Reserved)
11111000f0PUSH fPush f on top of stack
11111001f0POP fPop f from top of stack
1111101000kLNK #u14Push W14, W14 ← W15, W15 += k
1111101010—0—ULNKW15 ← W14, pop W14
1111101100000dpsSE src,dstCZNdst ← sign_extend(src), copy bit 7 to bits 15:8
1111101110000dpsZE src,dst1Z0dst ← zero_extend(src), clear bits 15:8
1111110000kDISI #u14Disable interrupt for k+1 cycles
1111110100000d000sEXCH Ws,WdSwap contents of registers Ws, Wd
11111101010000000000sDAW.B WsCDecimal adjust based on C, DC
111111011B0000000000sSWAP[.B] WsSwap halves of Ws
1111111000—0—RESETSoftware reset
11111110010—0—kPWRSAV #u1Go into sleep or idle mode
11111110011—0—CLRWDTClear watchdog timer
11111110100—0—POP.SPop shadow registers (W0–3, part of PSR)
11111110101—0—PUSH.SPush shadow registers (W0–3, part of PSR)
1111111011—(Reserved)
11111111—NOPRNo operation (version #2)

References

  1. ↑ PIC10F200/202/204/206 Data Sheet (PDF). Microchip Technology. 2007. p. 52.
  2. ↑ http://www.emc.com.tw/eng/products.asp
  3. ↑ ELAN Microelectronics Corp. (September 2005), EM78P157N 8-bit microcontroller with OTP ROM Product Specification (PDF), retrieved 2012-04-02
  4. ↑ "Introducing the Enhanced Mid-Range Architecture" (PDF). Microchip.
  5. ↑ http://www.microchipc.com/sourcecode/
  6. ↑ Microchip Technology, Inc. (2007), PIC18F1220/1320 Data Sheet (PDF), retrieved 2012-04-02
  7. ↑
  8. ↑ dsPIC30F Programmer's Reference Manual (PDF), Microchip Technology, 2008, DS70157C, retrieved 2012-07-02
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