Neuromorphic engineering

Neuromorphic engineering, also known as neuromorphic computing,[1][2][3] is a concept developed by Carver Mead,[4] in the late 1980s, describing the use of very-large-scale integration (VLSI) systems containing electronic analog circuits to mimic neuro-biological architectures present in the nervous system.[5] In recent times the term neuromorphic has been used to describe analog, digital, mixed-mode analog/digital VLSI, and software systems that implement models of neural systems (for perception, motor control, or multisensory integration). The implementation of neuromorphic computing on the hardware level can be realized by oxide-based memristors,[6] threshold switches, and transistors.[7]

A key aspect of neuromorphic engineering is understanding how the morphology of individual neurons, circuits, applications, and overall architectures creates desirable computations, affects how information is represented, influences robustness to damage, incorporates learning and development, adapts to local change (plasticity), and facilitates evolutionary change.

Neuromorphic engineering is an interdisciplinary subject that takes inspiration from biology, physics, mathematics, computer science, and electronic engineering to design artificial neural systems, such as vision systems, head-eye systems, auditory processors, and autonomous robots, whose physical architecture and design principles are based on those of biological nervous systems.[8]

Examples

As early as 2006, researchers at Georgia Tech published a field programmable neural array.[9] This chip was the first in a line of increasingly complex arrays of floating gate transistors that allowed programmability of charge on the gates of MOSFETs to model the channel-ion characteristics of neurons in the brain and was one of the first cases of a silicon programmable array of neurons.

In November 2011, a group of MIT researchers created a computer chip that mimics the analog, ion-based communication in a synapse between two neurons using 400 transistors and standard CMOS manufacturing techniques.[10][11]

In June 2012, spintronic researchers at Purdue presented a paper on the design of a neuromorphic chip using lateral spin valves and memristors. They argue that the architecture works similarly to neurons and can therefore be used to test methods of reproducing the brain's processing. In addition, these chips are significantly more energy-efficient than conventional ones.[12]

Research at HP Labs on Mott memristors has shown that while they can be non-volatile, the volatile behavior exhibited at temperatures significantly below the phase transition temperature can be exploited to fabricate a neuristor,[13] a biologically-inspired device that mimics behavior found in neurons.[13] In September 2013 they presented models and simulations that show how the spiking behavior of these neuristors can be used to form the components required for a Turing machine.[14]

Neurogrid, built by Brains in Silicon at Stanford University,[15] is an example of hardware designed using neuromorphic engineering principles. The circuit board is composed of 16 custom-designed chips, referred to as NeuroCores. Each NeuroCore's analog circuitry is designed to emulate neural elements for 65536 neurons, maximizing energy efficiency. The emulated neurons are connected using digital circuitry designed to maximize spiking throughput.[16][17]

A research project with implications for neuromorphic engineering is the Human Brain Project, a 10-year collaboration that is attempting to simulate a complete human brain in a supercomputer using biological data. It is made up of a group of researchers in neuroscience, medicine, and computing.[18] Henry Markram, the project's co-director, has stated that the project proposes to establish a foundation to explore and understand the brain and its diseases, and to use that knowledge to build new computing technologies. The three primary goals of the project are to better understand how the pieces of the brain fit and work together, to understand how to objectively diagnose and treat brain diseases, and to use the understanding of the human brain to develop neuromorphic computers. That the simulation of a complete human brain will require a supercomputer a thousand times more powerful than today's encourages the current focus on neuromorphic computers.[19] $1.3 billion has been allocated to the project by The European Commission.[20]

Other research with implications for neuromorphic engineering involves the BRAIN Initiative[21] and the TrueNorth chip from IBM.[22] Neuromorphic devices have also been demonstrated using nanocrystals, nanowires, and conducting polymers.[23]

Intel unveiled its neuromorphic research chip, called "Loihi", in October 2017. The chip uses an asynchronous spiking neural network (SNN) to implement adaptive self-modifying event-driven fine-grained parallel computations used to implement learning and inference with high efficiency.[24][25]

Neuromemristive systems

Neuromemristive systems are a subclass of neuromorphic computing systems that focus on the use of memristors to implement neuroplasticity. While neuromorphic engineering focuses on mimicking biological behavior, neuromemristive systems focus on abstraction.[26] For example, a neuromemristive system may replace the details of a cortical microcircuit's behavior with an abstract neural network model.[27]

There exist several neuron inspired threshold logic functions[6] implemented with memristors that have applications in high level pattern recognition applications. Some of the applications reported in recently include speech recognition,[28] face recognition[29] and object recognition.[30] They also find applications in replacing conventional digital logic gates.[31][32]

For ideal passive memristive circuits, it is possible to derive a differential equation for evolution of the internal memory of the circuit:[33]

as a function of the properties of the physical memristive network and the external sources. In the equation above, is the "forgetting" time scale constant, and is the ratio of off and on values of the limit resistances of the memristors, is the vector of the sources of the circuit and is a projector on the fundamental loops of the circuit. The diagonal matrix and vector and respectively, are instead the internal value of the memristors, with values between 0 and 1. This equation thus requires to add extra constraints on the memory values in order to be reliable.

See also

References

  1. ↑ Monroe, D. (2014). "Neuromorphic computing gets ready for the (really) big time". Communications of the ACM. 57 (6): 13–15. doi:10.1145/2601069.
  2. ↑ Zhao, W. S.; Agnus, G.; Derycke, V.; Filoramo, A.; Bourgoin, J. -P.; Gamrat, C. (2010). "Nanotube devices based crossbar architecture: Toward neuromorphic computing". Nanotechnology. 21 (17): 175202. Bibcode:2010Nanot..21q5202Z. doi:10.1088/0957-4484/21/17/175202. PMID 20368686.
  3. ↑ The Human Brain Project SP 9: Neuromorphic Computing Platform on YouTube
  4. ↑ Mead, Carver. "carver mead website". carvermead.
  5. ↑ Mead, Carver (1990). "Neuromorphic electronic systems". Proceedings of the IEEE. 78 (10): 1629–1636. doi:10.1109/5.58356.
  6. 1 2 Maan, A. K.; Jayadevi, D. A.; James, A. P. (2016-01-01). "A Survey of Memristive Threshold Logic Circuits". IEEE Transactions on Neural Networks and Learning Systems. PP (99): 1–13. arXiv:1604.07121. doi:10.1109/TNNLS.2016.2547842. ISSN 2162-237X.
  7. ↑ Zhou, You; Ramanathan, S. (2015-08-01). "Mott Memory and Neuromorphic Devices". Proceedings of the IEEE. 103 (8): 1289–1310. doi:10.1109/JPROC.2015.2431914. ISSN 0018-9219.
  8. ↑ Boddhu, S. K.; Gallagher, J. C. (2012). "Qualitative Functional Decomposition Analysis of Evolved Neuromorphic Flight Controllers". Applied Computational Intelligence and Soft Computing. 2012: 1–21. doi:10.1155/2012/705483.
  9. ↑ Farquhar, Ethan; Hasler, Paul. (May 2006). "A field programmable neural array". IEEE International Symposium on Circuits and Systems.
  10. ↑ "MIT creates "brain chip"". Retrieved 4 December 2012.
  11. ↑ "Neuromorphic silicon neurons and large-scale neural networks: challenges and opportunities". Frontiers in Neuroscience. 5. doi:10.3389/fnins.2011.00108. Retrieved 4 December 2012.
  12. ↑ Sharad, Mrigank; Augustine, Charles; Panagopoulos, Georgios; Roy, Kaushik (2012). "Proposal For Neuromorphic Hardware Using Spin Devices". arXiv:1206.3227 [cond-mat.dis-nn].
  13. 1 2 Pickett, M. D.; Medeiros-Ribeiro, G.; Williams, R. S. (2012). "A scalable neuristor built with Mott memristors". Nature Materials. 12 (2): 114–7. Bibcode:2013NatMa..12..114P. doi:10.1038/nmat3510. PMID 23241533.
  14. ↑ Matthew D Pickett and R Stanley Williams 2013 Nanotechnology 24 384002
  15. ↑ Boahen, Kwabena (24 April 2014). "Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations". Proceedings of the IEEE. 102 (5): 699–716. doi:10.1109/JPROC.2014.2313565.
  16. ↑ Waldrop, M. Mitchell (2013). "Neuroelectronics: Smart connections". Nature. 503 (7474): 22–4. Bibcode:2013Natur.503...22W. doi:10.1038/503022a. PMID 24201264.
  17. ↑ Benjamin, Ben Varkey; Peiran Gao; McQuinn, Emmett; Choudhary, Swadesh; Chandrasekaran, Anand R.; Bussat, Jean-Marie; Alvarez-Icaza, Rodrigo; Arthur, John V.; Merolla, Paul A.; Boahen, Kwabena (2014). "Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations". Proceedings of the IEEE. 102 (5): 699–716. doi:10.1109/JPROC.2014.2313565.
  18. ↑ "Involved Organizations". Archived from the original on 2 March 2013. Retrieved 22 February 2013.
  19. ↑ "Human Brain Project". Retrieved 22 February 2013.
  20. ↑ "The Human Brain Project and Recruiting More Cyberwarriors". Retrieved 22 February 2013.
  21. ↑ Neuromorphic computing: The machine of a new soul, The Economist, 2013-08-03
  22. ↑ Modha, Dharmendra (Aug 2014). "A million spiking-neuron integrated circuit with a scalable communication network and interface". Science. 345 (6197): 668–673. Bibcode:2014Sci...345..668M. doi:10.1126/science.1254642. PMID 25104385.
  23. ↑ Fairfield, Jessamyn (March 1, 2017). "Smarter Machines" (PDF).
  24. ↑ Davies, Mike; et al. (January 16, 2018). "Loihi: A Neuromorphic Manycore Processor with On-Chip Learning". IEEE Micro. 38 (1): 82–99. Retrieved August 5, 2018.
  25. ↑ Morris, John. "Why Intel built a neuromorphic chip | ZDNet". ZDNet. ZDNet. Retrieved 17 August 2018.
  26. ↑ D. Kudithipudi, "Towards intelligent computing with neuromemristive circuits and systems," Sandia NICE Workshop, 2014, http://digitalops.sandia.gov/Mediasite/Play/a10cf6ceb55d47608bb8326dd00e46611d
  27. ↑ C. Merkel and D. Kudithipudi, "Neuromemristive extreme learning machines for pattern classification," ISVLSI, 2014.
  28. ↑ Maan, A.K.; James, A.P.; Dimitrijev, S. (2015). "Memristor pattern recogniser: isolated speech word recognition". Electronics Letters. 51 (17): 1370–1372. doi:10.1049/el.2015.1428.
  29. ↑ Maan, Akshay Kumar; Kumar, Dinesh S.; James, Alex Pappachen (2014-01-01). "Memristive Threshold Logic Face Recognition". Procedia Computer Science. 5th Annual International Conference on Biologically Inspired Cognitive Architectures, 2014 BICA. 41: 98–103. doi:10.1016/j.procs.2014.11.090.
  30. ↑ Maan, A.K.; Kumar, D.S.; Sugathan, S.; James, A.P. (2015-10-01). "Memristive Threshold Logic Circuit Design of Fast Moving Object Detection". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23 (10): 2337–2341. arXiv:1410.1267. doi:10.1109/TVLSI.2014.2359801. ISSN 1063-8210.
  31. ↑ James, A.P.; Francis, L.R.V.J.; Kumar, D.S. (2014-01-01). "Resistive Threshold Logic". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22 (1): 190–195. arXiv:1308.0090. doi:10.1109/TVLSI.2012.2232946. ISSN 1063-8210.
  32. ↑ James, A.P.; Kumar, D.S.; Ajayan, A. (2015-11-01). "Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23 (11): 2690–2694. arXiv:1411.5255. doi:10.1109/TVLSI.2014.2371857. ISSN 1063-8210.
  33. ↑ Caravelli; et al. (2 Nov 2016). "The complex dynamics of memristive circuits: analytical results and universal slow relaxation". Physical Review E. 95. arXiv:1608.08651 [cond-mat.dis-nn]. Bibcode:2017PhRvE..95b2140C. doi:10.1103/PhysRevE.95.022140. Cite uses deprecated parameter |class= (help)
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