FMA instruction set

The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations.[1] There are two variants:

New instructions

FMA3 and FMA4 instructions have almost identical functionality but are not compatible. Both contain fused multiply–add (FMA) instructions for floating point scalar and SIMD operations, but FMA3 instructions have three operands while FMA4 ones have four. The FMA operation has the form d = round(a · b + c) where the round function performs a rounding to allow the result to fit within the destination register if there are too many significant bits to fit within the destination.

The four-operand form (FMA4) allows a, b, c and d to be four different registers, while the three-operand form (FMA3) requires that d be the same register as a, b or c. The three-operand form makes the code shorter and the hardware implementation slightly simpler while the four-operand form provides more programming flexibility.

See XOP instruction set for more discussion of compatibility issues between Intel and AMD.

FMA3 instruction set

CPUs with FMA3

  • AMD
    • AMD introduced FMA3 support in processors starting with Piledriver architecture for compatibility reasons.[2][3] The 2nd generation APU processors based on "Trinity" (32nm) supporting FMA3 instructions were launched May 15, 2012. The 2nd generation Bulldozer processors with Piledriver cores supporting FMA3 instructions were launched October 23, 2012.
  • Intel
    • Intel introduced hardware FMA3 in processors based on Haswell during 2013.

Excerpt from FMA3

Mnemonic (AT&T) Operands Operation
VFMADD132PDy ymm, ymm, ymm/m256 a = a·c + b
VFMADD132PSy
VFMADD132PDx xmm, xmm, xmm/m128
VFMADD132PSx
VFMADD132SD xmm, xmm, xmm/m64
VFMADD132SS xmm, xmm, xmm/m32
VFMADD213PDy ymm, ymm, ymm/m256 a = b·a + c
VFMADD213PSy
VFMADD213PDx xmm, xmm, xmm/m128
VFMADD213PSx
VFMADD213SD xmm, xmm, xmm/m64
VFMADD213SS xmm, xmm, xmm/m32
VFMADD231PDy ymm, ymm, ymm/m256 a = b·c + a
VFMADD231PSy
VFMADD231PDx xmm, xmm, xmm/m128
VFMADD231PSx
VFMADD231SD xmm, xmm, xmm/m64
VFMADD231SS xmm, xmm, xmm/m32

FMA4 instruction set

CPUs with FMA4

  • AMD
    • "Heavy Equipment" processors
    • Zen: WikiChip's testing shows FMA4 still appears to work (under the conditions of the tests) despite not being officially supported and not even reported by CPUID. This has also been confirmed by Agner.[6] But other tests gave wrong results.[7] AMD Official Web Site FMA4 Support Note ZEN CPUs = AMD ThreadRipper 1900x, R7 Pro 1800, 1700, R5 Pro 1600, 1500, R3 Pro 1300, 1200, R3 2200G, R5 2400G.[8][9][10]
  • Intel
    • It is uncertain whether future Intel processors will support FMA4, due to Intel's announced change to FMA3.

Excerpt from FMA4

Mnemonic (AT&T) Operands Operation
VFMADDPDx xmm, xmm, xmm/m128, xmm/m128 a = b·c + d
VFMADDPDy ymm, ymm, ymm/m256, ymm/m256
VFMADDPSx xmm, xmm, xmm/m128, xmm/m128
VFMADDPSy ymm, ymm, ymm/m256, ymm/m256
VFMADDSD xmm, xmm, xmm/m64, xmm/m64
VFMADDSS xmm, xmm, xmm/m32, xmm/m32

History

The incompatibility between Intel's FMA3 and AMD's FMA4 is due to both companies changing plans without coordinating coding details with each other. AMD changed their plans from FMA3 to FMA4 while Intel changed their plans from FMA4 to FMA3 almost at the same time. The history can be summarized as follows:

  • August 2007: AMD announces the SSE5 instruction set, which includes 3-operand FMA instructions. A new coding scheme (DREX) is introduced for allowing instructions to have three operands.[11]
  • April 2008: Intel announces their AVX and FMA instruction sets, including 4-operand FMA instructions. The coding of these instructions uses the new VEX coding scheme,[12] which is more flexible than AMD's DREX scheme.
  • December 2008: Intel changes the specification for their FMA instructions from 4-operand to 3-operand instructions. The VEX coding scheme is still used.[13]
  • May 2009: AMD changes the specification of their FMA instructions from the 3-operand DREX form to the 4-operand VEX form, compatible with the April 2008 Intel specification rather than the December 2008 Intel specification.[14]
  • October 2011: AMD Bulldozer processor supports FMA4.[15]
  • January 2012: AMD announces FMA3 support in future processors codenamed Trinity and Vishera; they are based on the Piledriver architecture.[16]
  • May 2012: AMD Piledriver processor supports both FMA3 and FMA4.[15]
  • June 2013: Intel Haswell processor supports FMA3.[17]
  • February 2017 The first generation of AMD Ryzen processors officially supports FMA3, but not FMA4 according to the CPUID instruction.[18] There has been confusion regarding whether FMA4 was implemented or not on this processor due to errata in the initial patch to the GNU Binutils package that has since been rectified.[19][20] While the FMA4 instructions seem to work according to some tests, they can also give wrong results.[7] Additionally, the initial Ryzen CPUs could be crashed by a particular sequence of FMA3 instructions. It has since been resolved by an updated CPU microcode.[21]

Compiler and assembler support

Different compilers provide different levels of support for FMA4:

References

  1. ↑ "FMA3 and FMA4 are not instruction sets, they are individual instructions -- fused multiply add. They could be quite useful depending on how Intel and AMD implement them" Woltmann, George (Prime95). "Intel AVX and GIMPS". mersenneforum.org/index.php. Great Internet Mersenne Prime Search (GIMPS) project. Retrieved 27 July 2011.
  2. ↑ "Striking a balance". Dave Christie, AMD Developer blogs. May 7, 2009. Retrieved 2009-05-08.
  3. ↑ Maffeo, Robin. "AMD and the Visual Studio 11 Beta". AMD. Retrieved 19 April 2012.
  4. ↑ "AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions" (PDF). AMD. May 1, 2009.
  5. ↑ "New "Bulldozer" and "Piledriver" Instructions A step forward for high performance software development" (PDF). AMD. October 2012.
  6. ↑ http://agner.org/optimize/blog/read.php?i=838
  7. 1 2 "Discussion – Ryzen has undocumented support for FMA4". Retrieved 2017-05-10.
  8. ↑ "www.amd.com, FMA4 support model list".
  9. ↑ "www.amd.com, FMA4 support model list".
  10. ↑ "www.amd.com, FMA4 support model list".
  11. ↑ "128-Bit SSE5 Instruction Set". AMD Developer Central. Archived from the original on 2008-01-15. Retrieved 2008-01-28.
  12. ↑ "Intel Advanced Vector Extensions Programming Reference" (PDF). Intel. Retrieved 2008-04-05.
  13. ↑ "Intel Advanced Vector Extensions Programming Reference". Intel. Retrieved 2009-05-06.
  14. ↑ "Striking a balance". Dave Christie, AMD Developer blogs. May 7, 2009. Retrieved 2009-05-08.
  15. 1 2 "New Bulldozer and Piledriver Instructions" (PDF). AMD. Retrieved 25 July 2013.
  16. ↑ "Software Optimization Guide for AMD Family 15h Processors" (PDF). AMD. Retrieved 19 April 2012.
  17. ↑ "Intel Architecture Instruction Set Extensions Programming Reference" (PDF). Intel. Retrieved 25 July 2013.
  18. ↑ "The microarchitecture of Intel, AMD and VIA CPUs An optimization guide for assembly programmers and compiler makers" (PDF). Retrieved 2017-05-02.
  19. ↑ https://sourceware.org/ml/binutils/2015-03/msg00078.html
  20. ↑ https://sourceware.org/ml/binutils/2015-08/msg00039.html
  21. ↑ "AMD Ryzen Machine Crashes to a Sequence of FMA3 Instructions". Retrieved 2017-09-10.
  22. 1 2 Latif, Lawrence (Nov 14, 2011). "AMD Bulldozer only FMA4 and XOP instructions are supported by GCC Intel still mute". The Inquirer.
  23. ↑ "FMA4 Intrinsics Added for Visual Studio 2010 SP1".
  24. ↑ "EKOPath man doc".
  25. ↑ "LLVM 3.1 Release Notes".
  26. ↑ "Enable detection of AVX and AVX2 support through CPUID". LLVM. 2012-04-26.
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