FLAGS register

The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the processor. This register is 16 bits wide. Its successors, the EFLAGS and RFLAGS registers, are 32 bits and 64 bits wide, respectively. The wider registers retain compatibility with their smaller predecessors.

The fixed bits at bit positions 1, 3 and 5, and carry, parity, adjust, zero and sign flags are inherited from an even earlier architecture, 8080. The adjust flag used to be called auxiliary carry bit in 8080 and half-carry bit in the Zilog Z80 architecture.

FLAGS

Intel x86 FLAGS register[1]
Bit #MaskAbbreviationDescriptionCategory
FLAGS
00x0001CFCarry flagStatus
10x0002Reserved, always 1 in EFLAGS [2] 
20x0004PFParity flagStatus
30x0008Reserved 
40x0010AFAdjust flagStatus
50x0020Reserved 
60x0040ZFZero flagStatus
70x0080SFSign flagStatus
80x0100TFTrap flag (single step)Control
90x0200IFInterrupt enable flagControl
100x0400DFDirection flagControl
110x0800OFOverflow flagStatus
12-130x3000IOPLI/O privilege level (286+ only),
always 1 on 8086 and 186		System
140x4000NTNested task flag (286+ only),
always 1 on 8086 and 186		System
150x8000Reserved,
always 1 on 8086 and 186,
always 0 on later models		 
EFLAGS
160x0001 0000RFResume flag (386+ only)System
170x0002 0000VMVirtual 8086 mode flag (386+ only)System
180x0004 0000ACAlignment check (486SX+ only)System
190x0008 0000VIFVirtual interrupt flag (Pentium+)System
200x0010 0000VIPVirtual interrupt pending (Pentium+)System
210x0020 0000IDAble to use CPUID instruction (Pentium+)System
220x0040 0000IDAble to use CPUID instruction (Pentium+)System
23-310xFF80 0000VADVAD FlagSystem
RFLAGS
32-630xFFFF FFFF...
...0000 0000		Reserved 

Note: The mask column in the table is the AND bitmask (as hexadecimal value) to query the flag(s) within FLAGS register value.

Usage

The POPF, POPFD, and POPFQ instructions read from the stack, the first 16, 32, and 64 bits of the flags register, respectively. POPFD was introduced with the i386 architecture and POPFQ with the x64 architecture. In 64-bit mode, PUSHF/POPF and PUSHFQ/POPFQ are available but not PUSHFD/POPFD.[3]

The following assembly code changes the direction flag (DF):

pushf ; Pushes the current flags onto the stack
pop ax ; Pop the flags from the stack into ax register
push ax ; Push them back onto the stack for storage
xor ax, 400h ; toggle the DF flag only, keep the rest of the flags
push ax ; Push again to add the new value to the stack
popf ; Pop the newly pushed into the FLAGS register
; ... Code here ...
popf ; Pop the old FLAGS back into place

In practical software, the cld and std instructions are used to clear and set the direction flag, respectively. Some instructions in assembly language use the FLAGS register. The conditional jump instructions use certain flags to compute. For example, jz uses the zero flag, jc uses the carry flag and jo uses the overflow flag. Other conditional instructions look at combinations of several flags.

Determination of processor type

Testing if certain bits in the FLAGS register are changeable allows determining what kind of processor is installed. For example, the alignment flag can only be changed on the 486 and above, so if it can be changed then the CPU is a 486 or higher. These methods of processor detection were not made obsolete by the CPUID instruction introduced with the Intel Pentium, as CPUID is not implemented in these older CPUs.

See also

References

  1. ↑ Intel 64 and IA-32 Architectures Software Developer's Manual (PDF). 1. May 2012. pp. 3–21.
  2. ↑ Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). 1. Dec 2016. p. 78.
  3. ↑ Intel 64 and IA-32 Architectures Software Developer’s Manual (PDF). 2B. May 2012. pp. 4–349, 4–432.
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