Accumulator: A

The Accumulator is implied as the operand, so no address needs to be specified.

Example

Using the ASL (Arithmetic Shift Left) instruction with no operands, the Accumulator is always the value being shifted left.

ASL

Implied: i

The operand is implied, so it does not need to be specified.

Example

The operands being implied here are X, the source of the transfer, and A, the destination of the transfer.

TXA

Immediate: #

The operand is used directly to perform the computation.

Example

The value $22 is loaded into the Accumulator.

LDA #$22

Absolute: a

A full 16-bit address is specified and the byte at that address is used to perform the computation.

Example

The value at address $D010 is loaded into the X register.

LDX $D010

Zero Page: zp

A single byte specifies an address in the first page of memory ($00xx), also known as the zero page, and the byte at that address is used to perform the computation.

Example

The value at address $0002 is loaded into the Y register.

LDY $02

Relative: r

The offset specified is added to the current address stored in the Program Counter (PC). Offsets can range from -128 to +127.

Example

The offset $2D is added to the address in the Program Counter (say $C100). The destination of the branch (if taken) will be $C12D.

BPL $2D

Absolute Indexed with X: a,x

The value in X is added to the specified address for a sum address. The value at the sum address is used to perform the computation.

Example

The value $02 in X is added to $C001 for a sum of $C003. The value $5A at address $C003 is used to perform the add with carry (ADC) operation.

ADC $C001,X

Absolute Indexed with Y: a,y

The value in Y is added to the specified address for a sum address. The value at the sum address is used to perform the computation.

Example

The value $03 in Y is added to $F001 for a sum of $F004. The value $EF at address $F004 is incremented (INC) and $F0 is written back to $F004.

INC $F001,Y

Zero Page Indexed with X: zp,x

The value in X is added to the specified zero page address for a sum address. The value at the sum address is used to perform the computation.

Example

The value $02 in X is added to $01 for a sum of $03. The value $A5 at address $0003 is loaded into the Accumulator.

LDA $01,X

Zero Page Indexed with Y: zp,y

The value in Y is added to the specified zero page address for a sum address. The value at the sum address is used to perform the computation.

Example

The value $03 in Y is added to $01 for a sum of $04. The value $E3 at address $0004 is loaded into the Accumulator.

LDA $01,Y

Zero Page Indexed Indirect: (zp,x)

The value in X is added to the specified zero page address for a sum address. The little-endian address stored at the two-byte pair of sum address (LSB) and sum address plus one (MSB) is loaded and the value at that address is used to perform the computation.

Example

The value $02 in X is added to $15 for a sum of $17. The address $D010 at addresses $0017 and $0018 will be where the value $0F in the Accumulator is stored.

STA ($15,X)

Zero Page Indirect Indexed with Y: (zp),y

The value in Y is added to the address at the little-endian address stored at the two-byte pair of the specified address (LSB) and the specified address plus one (MSB). The value at the sum address is used to perform the computation. Indeed addressing mode actually repeats exactly the Accumulator register's digits.

Example

The value $03 in Y is added to the address $C235 at addresses $002A and $002B for a sum of $C238. The Accumulator is then exclusive ORed with the value $2F at $C238.

EOR ($2A),Y

Load and Store

Load Accumulator with Memory: LDA

M -> A

Flags: N, Z

Load Index X with Memory: LDX

M -> X

Flags: N, Z

Load Index Y with Memory: LDY

M -> Y

Flags: N, Z

Store Accumulator in Memory: STA

A -> M

Flags: none

Store Index X in Memory: STX

X -> M

Flags: none

Store Index Y in Memory: STY

Y -> M

Flags: none

Arithmetic

Add Memory to Accumulator with Carry: ADC

A + M + C -> A

Flags: N, V, Z, C

Subtract Memory from Accumulator with Borrow: SBC

A - M - ~C -> A

Flags: N, V, Z, C

Increment and Decrement

Increment Memory by One: INC

M + 1 -> M

Flags: N, Z

Increment Index X by One: INX

X + 1 -> X

Flags: N, Z

Increment Index Y by One: INY

Y + 1 -> Y

Flags: N, Z

Decrement Memory by One: DEC

M - 1 -> M

Flags: N, Z

Decrement Index X by One: DEX

X - 1 -> X

Flags: N, Z

Decrement Index Y by One: DEY

Y - 1 -> Y

Flags: N, Z

Shift and Rotate

Arithmetic Shift Left One Bit: ASL

C <- 7 6 5 4 3 2 1 0 <- 0

Flags: N, Z, C

Logical Shift Right One Bit: LSR

0 -> 7 6 5 4 3 2 1 0 -> C

Flags: N, Z, C

Rotate Left One Bit: ROL

C <- 7 6 5 4 3 2 1 0 <- C

Flags: N, Z, C

Rotate Right One Bit: ROR

C -> 7 6 5 4 3 2 1 0 -> C

Flags: N, Z, C

Logic

AND Memory with Accumulator: AND

A & M -> A

Flags: N, Z

OR Memory with Accumulator: ORA

A | M -> A

Flags: N, Z

Exclusive-OR Memory with Accumulator: EOR

A ^ M -> A

Flags: N, Z

Compare and Test Bit

The CPU uses the following status flags. The Negative (N), Zero (Z), and Carry (C) flags are used for conditional (branch) instructions:

For all Compare instructions:

Compare Memory and Accumulator: CMP

A - M

Flags: N, Z, C

Compare Memory and Index X: CPX

X - M

Flags: N, Z, C

Compare Memory with Index Y: CPY

Y - M

Flags: N, Z, C

Test Bits in Memory with Accumulator: BIT

A & M

Flags: N = M7, V = M6, Z

Branch

Branch on Carry Clear: BCC

Branch if C = 0

Flags: none

Branch on Carry Set: BCS

Branch if C = 1

Flags: none

Branch on Result Zero: BEQ

Branch if Z = 1

Flags: none

Branch on Result Minus: BMI

Branch if N = 1

Flags: none

Branch on Result not Zero: BNE

Branch if Z = 0

Flags: none

Branch on Result Plus: BPL

Branch if N = 0

Flags: none

Branch on Overflow Clear: BVC

Branch if V = 0

Flags: none

Branch on Overflow Set: BVS

Branch if V = 1

Flags: none

Transfer

Transfer Accumulator to Index X: TAX

A -> X

Flags: N, Z

Transfer Index X to Accumulator: TXA

X -> A

Flags: N, Z

Transfer Accumulator to Index Y: TAY

A -> Y

Flags: N, Z

Transfer Index Y to Accumulator: TYA

Y -> A

Flags: N, Z

Transfer Stack Pointer to Index X: TSX

S -> X

Flags: N, Z

Transfer Index X to Stack Pointer: TXS

X -> S

Flags: none

Stack

Push Accumulator on Stack: PHA

A -> S

Flags: none

Pull Accumulator from Stack: PLA

S -> A

Flags: N, Z

Push Processor Status on Stack: PHP

P -> S

The processor status is stored as a single byte with the following flags bits from high to low: NV--DIZC.

Flags: none

Pull Processor Status from Stack: PLP

S -> P

Flags: all

Subroutines and Jump

Jump to New Location: JMP

Jump to new location

Flags: none

Jump to New Location Saving Return Address: JSR

Jump to Subroutine

Flags: none

Return from Subroutine: RTS

Return from Subroutine

Flags: none

Return from Interrupt: RTI

Return from Interrupt

Flags: all

Set and Clear

Set Carry Flag: SEC

1 -> C

Flags: C = 1

Set Decimal Mode: SED

1 -> D

Flags: D = 1

Set Interrupt Disable Status: SEI

1 -> I

Flags: I = 1

Clear Carry Flag: CLC

0 -> C

Flags: C = 0

Clear Decimal Mode: CLD

0 -> D

Flags: D = 0

Clear Interrupt Disable Status: CLI

0 -> I

Flags: I = 0

Clear Overflow Flag: CLV

0 -> V

Flags: V = 0

Miscellaneous

No Operation: NOP

No Operation

Flags: none

Break: BRK

Force an Interrupt

Flags: B = 1, I = 1