Makefile

Most often, the makefile directs Make on how to compile and link a program. A makefile works upon the principle that files only need recreating if their dependencies are newer than the file being created/recreated. The makefile is recursively carried out (with dependency prepared before each target depending upon them) until everything has been updated (that requires updating) and the primary/ultimate target is complete. These instructions with their dependencies are specified in a makefile. If none of the files that are prerequisites have been changed since the last time the program was compiled, no actions take place. For large software projects, using Makefiles can substantially reduce build times if only a few source files have changed.

Using C/C++ as an example, when a C/C++ source file is changed, it must be recompiled. If a header file has changed, each C/C++ source file that includes the header file must be recompiled to be safe. Each compilation produces an object file corresponding to the source file. Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable program.[1]

Makefiles contain five kinds of things: explicit rules, implicit rules, variable definitions, directives, and comments.

• An explicit rule says when and how to remake one or more files, called the rule's targets. It lists the other files that the targets depend on, called the prerequisites of the target, and may also give a recipe to use to create or update the targets.
• An implicit rule says when and how to remake a class of files based on their names. It describes how a target may depend on a file with a name similar to the target and gives a recipe to create or update such a target.
• A variable definition is a line that specifies a text string value for a variable that can be substituted into the text later.
• A directive is an instruction for make to do something special while reading the makefile such as reading another makefile.
• ‘#’ in a line of a makefile starts a comment. It and the rest of the line is ignored.

A makefile consists of “rules” in the following form:

target: dependencies
    system command(s)

A target is usually the name of a file that is generated by a program; examples of targets are executable or object files. A target can also be the name of an action to carry out, such as "clean".

A dependency (also called prerequisite) is a file that is used as input to create the target. A target often depends on several files. However, the rule that specifies a recipe for the target need not have any prerequisites. For example, the rule containing the delete command associated with the target "clean" does not have prerequisites.

The system command(s) (also called recipe) is an action that make carries out. A recipe may have more than one command, either on the same line or each on its own line. Note the use of meaningful indentation in specifying commands; also note that the indentation must consist of a single <tab> character.

A makefile is executed with the make command, e.g. make [options] [target1 target2 ...]. By default, when make looks for the makefile, if a makefile name was not included as a parameter, it tries the following names, in order: makefile and Makefile.[1]

Here is a makefile that describes the way an executable file called edit depends on four object files which, in turn, depend on four C source and two header files. To be concrete, edit is a target, edit.o, kbd.o, command.o and display.o are the objects we link to make the executable, defs.h and command.h are headers that our objects need to compile correctly, and $(CC) -c -o $@ $< $(CCFLAGS) is a system command.

• $@ is a macro that refers to the target
• $< is a macro that refers to the first dependency
• $^ is a macro that refers to all dependencies
• % is a macro to make a pattern that we want to watch in both the target and the dependency

The make file will recompile all objects if any of the headers change, but if an individual .c file changes, the only work that will need to be done is to recompile that file and then relink all the objects. Well written make rules can help reduce compile time by detecting what did and did not change

Notice the way the variables and static pattern rules are used to make the makefile more extensible and readable. We define the same, reusable rule to make each .o from each .c, and to make each target from the objects.

Also notice that we can only link one main at a time, so we have to filter out other mains at linking.

The targets all and clean are named .PHONY because they don't refer to real files, but are things we want make to do.

CC      := gcc
CCFLAGS := 
LDFLAGS :=

TARGETS:= edit
MAINS  := $(addsuffix .o, $(TARGETS) )
OBJ    := kbd.o command.o display.o $(MAINS)
DEPS   := defs.h command.h

.PHONY: all clean

all: $(TARGETS)

clean:
	rm -f $(TARGETS) $(OBJ)

$(OBJ): %.o : %.c $(DEPS)
	$(CC) -c -o $@ $< $(CCFLAGS)

$(TARGETS): % : $(filter-out $(MAINS), $(OBJ)) %.o
	$(CC) -o $@ $(LIBS) $^ $(CCFLAGS) $(LDFLAGS)

To use this makefile to create the executable file called edit, type make allor make edit. To use this makefile to delete the executable file and all the object files from the directory, type make clean.

• Make (software)