Resistive random-access memory

Resistive random-access memory (ReRAM or RRAM) is a type of non-volatile (NV) random-access (RAM) computer memory that works by changing the resistance across a dielectric solid-state material, often referred to as a memristor. This technology bears some similarities to conductive-bridging RAM (CBRAM), and phase-change memory (PCM).

CBRAM involves one electrode providing ions that dissolve readily in an electrolyte material, while PCM involves generating sufficient Joule heating to effect amorphous-to-crystalline or crystalline-to-amorphous phase changes. On the other hand, ReRAM involves generating defects in a thin oxide layer, known as oxygen vacancies (oxide bond locations where the oxygen has been removed), which can subsequently charge and drift under an electric field. The motion of oxygen ions and vacancies in the oxide would be analogous to the motion of electrons and holes in a semiconductor.

ReRAM is currently under development by a number of companies, some of which have filed patent applications claiming various implementations of this technology.[1][2][3] ReRAM has entered commercialization on an initially limited KB-capacity scale.[4]

Although ReRAM was initially seen as a replacement technology for flash memory, the cost and performance benefits of ReRAM have not been enough for companies to proceed with the replacement. Apparently, a broad range of materials can be used for ReRAM. However, the discovery[5] that the popular high-κ gate dielectric HfO2 can be used as a low-voltage ReRAM has encouraged researchers to investigate more possibilities. Among these, SiOx has been found to offer significant benefits and is currently being explored by some companies such as Weebit-Nano Ltd.

RRAM® is the registered trademark name of Sharp Corporation, one of Japanese electronic components manufacturer, in some countries including EU.[6]

History

In February 2012, Rambus bought a ReRAM company called Unity Semiconductor for $35 million.[7] Panasonic launched an ReRAM evaluation kit in May 2012, based on a tantalum oxide 1T1R (1 transistor – 1 resistor) memory cell architecture.[8]

In 2013, Crossbar introduced an ReRAM prototype as a chip about the size of a postage stamp that could store 1 TB of data. In August 2013, the company claimed that large-scale production of their ReRAM chips was scheduled for 2015.[9] The memory structure (Ag/a-Si/Si) closely resembles a silver-based CBRAM.

Different forms of ReRAM have been disclosed, based on different dielectric materials, spanning from perovskites to transition metal oxides to chalcogenides. Silicon dioxide was shown to exhibit resistive switching as early as May 1966,[10] and has recently been revisited.[11][12]

In 1963 and 1964, a thin-film resistive memory array was first proposed by members of University of Nebraska–Lincoln.[13][14] Since August 1967, this new thin-film resistive memory has been presented by J.G. Simmons.[15][16] In 1970, member of Atomic Energy Research Establishment and University of Leeds tried to explain the mechanism theoretically.[17]:1180 In May 1997, a research team of University of Florida and Honeywell reported a manufacturing method for "magneto-resistive random access memory" by utilizing electron cyclotron resonance plasma etching.[18]

Leon Chua argued that all two-terminal non-volatile memory devices including ReRAM should be considered memristors.[19] Stan Williams of HP Labs also argued that ReRAM was a memristor.[20] However, others challenged this terminology and the applicability of memristor theory to any physically realizable device is open to question.[21][22] Whether redox-based resistively switching elements (ReRAM) are covered by the current memristor theory is disputed.[23]

Silicon oxide presents an interesting case of resistance switching. Two distinct modes of intrinsic switching have been reported - surface-based, in which conductive silicon filaments are generated at exposed edges (which may be internal - within pores - or external - on the surface of mesa structures), and bulk switching, in which oxygen vacancy filaments are generated within the bulk of the oxide. The former mode suffers from oxidation of the filaments in air, requiring hermetic sealing to enable switching. The latter requires no sealing. In 2014 researchers from Rice University announced a silicon filament-based device that used a porous silicon oxide dielectric with no external edge structure - rather, filaments were formed at internal edges within pores. Devices can be manufactured at room temperature and have a sub-2V forming voltage, high on-off ratio, low power consumption, nine-bit capacity per cell, high switching speeds and good endurance. Problems with their inoperability in air can be overcome by hermetic sealing of devices[24]. Bulk switching in silicon oxide, pioneered by researchers at UCL (University College London) since 2012[25], offers low electroforming voltages (2.5V), switching voltages around 1V, switching times in the nanoseconds regime, and more than 10,000,000 cycles without device failure - all in ambient conditions.[26]

Forming

Filament forming: A 50 nm × 50 nm ReRAM cell by Crossbar shows the instance of filament forming when the current abruptly increases beyond a certain voltage. A transistor is often used to limit current to prevent a runaway breakdown following the filament formation.

The basic idea is that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after application of a sufficiently high voltage.[27] The conduction path can arise from different mechanisms, including vacancy or metal defect migration. Once the filament is formed, it may be reset (broken, resulting in high resistance) or set (re-formed, resulting in lower resistance) by another voltage. Many current paths, rather than a single filament, are possibly involved.[28] The presence of these current paths in the dielectric can be in situ demonstrated via conductive atomic force microscopy.[27][29][30][31]

The low-resistance path can be either localized (filamentary) or homogeneous. Both effects can occur either throughout the entire distance between the electrodes or only in proximity to one of the electrodes. Filamentary and homogenous switching effects can be distinguished by measuring the area dependence of the low-resistance state.[32]

Under certain conditions, the forming operation may be bypassed.[33] It is expected that under these conditions, the initial current is already quite high compared to insulating oxide layers.

CBRAM cells generally would not require forming if Cu ions are already present in the electrolyte, having already been driven-in by a designed photo-diffusion or annealing process; such cells may also readily return to their initial state.[34] In the absence of such Cu initially being in the electrolyte, the voltage would still be applied directly to the electrolyte, and forming would be a strong possibility.[35]

Operation styles

For random-access type memories, a 1T1R (one transistor, one resistor) architecture is preferred because the transistor isolates current to cells that are selected from cells that are not. On the other hand, a cross-point architecture is more compact and may enable vertically stacking memory layers, ideally suited for mass-storage devices. However, in the absence of any transistors, isolation must be provided by a "selector" device, such as a diode, in series with the memory element or by the memory element itself. Such isolation capabilities are inferior to the use of transistors if the on/off ratio for the selector is not sufficient, limiting the ability to operate very large arrays in this architecture. Thin film based threshold switch can work as a selector for bipolar and unipolar ReRAM. Threshold switch-based selector was demonstrated for 64 Mb array.[36] However, One shouldn't forget that the cross-point architecture requires BEOL compatible two terminal selectors like punch-through diode for bipolar ReRAM[37] or PIN diode for unipolar ReRAM.[38]

Polarity can be either binary or unary. Bipolar effects cause polarity to reverse when switching from low to high resistance (reset operation) compared to switching high to low (set operation). Unipolar switching leaves polarity unaffected, but uses different voltages.

Material systems for resistive memory cells

Multiple inorganic and organic material systems display thermal or ionic resistive switching effects. These can be grouped into the following categories:[32]

  • phase-change chalcogenides such as Ge
    2    Sb
    2    Te
    5     or AgInSbTe
  • binary transition metal oxides such as NiO or TiO
    2
  • perovskites such as Sr(Zr)TiO
    3    [39] or PCMO
  • solid-state electrolytes such as GeS, GeSe, SiO
    x     or Cu
    2    S
  • organic charge-transfer complexes such as CuTCNQ
  • organic donor–acceptor systems such as Al AIDCN
  • two dimensional (layered) insulating materials like hexagonal boron nitride[40][41]

Demonstrations

Papers at the IEDM Conference in 2007 suggested for the first time that ReRAM exhibits lower programming currents than PRAM or MRAM without sacrificing programming performance, retention or endurance.[42] Some commonly cited ReRAM systems are described further below.

HfO2-based ReRAM

At IEDM 2008, the highest-performance ReRAM technology to date was demonstrated by ITRI using HfO2 with a Ti buffer layer, showing switching times less than 10 ns and currents less than 30μA. At IEDM 2010, ITRI again broke the speed record, showing <0.3 ns switching time, while also showing process and operation improvements to allow yield up to 100% and endurance up to 10 billion cycles.[43] IMEC presented updates of their ReRAM program at the 2012 Symposia on VLSI Technology and Circuits, including a solution with a 500 nA operating current.[44]

ITRI had focused on the Ti/HfO2 system since its first publication in 2008. ITRI's patent 8362454 has since been sold to TSMC;[45] the number of prior licensees is unknown. On the other hand, IMEC focused mainly on Hf/HfO2.[46] Winbond had done more recent work toward advancing and commercializing the HfO2-based ReRAM.[47]

Panasonic

Panasonic revealed its TaOx-based ReRAM at IEDM 2008.[48] A key requirement was the need for a high work function metal such as Pt or Ir to interface with the TaOx layer. The change of O content results in resistance change as well as Schottky barrier change. More recently, a Ta2O5/TaOx layer was implemented, which still requires the high work function metal to interface with Ta2O5.[49] This system has been associated with high endurance demonstration (trillion cycles),[50] but products are specified at 100K cycles.[51] Filament diameters as large as ~100 nm have been observed.[52] Panasonic released a 4Mb part with Fujitsu,[53] and is developing 40nm embedded memory with UMC.[54]

HP Memristor

On 30 April 2008, HP announced that they had discovered the memristor, originally envisioned as a missing 4th fundamental circuit element by Chua in 1971. On 8 July they announced they would begin prototyping ReRAM using their memristors.[55] HP first demonstrated its memristor using TiOx,[56] but later migrated to TaOx,[57] possibly due to improved stability.[58] The TaOx-based device has some material similarity to Panasonic's ReRAM, but the operation characteristics are different. The Hf/HfOx system was similarly studied.[59]

Adesto Technologies

The Adesto Technologies ReRAM is based on filaments generated from the electrode metal rather than oxygen vacancies. The original material system was Ag/GeS2[60] but eventually migrated to ZrTe/Al2O3.[61] The tellurium filament achieved better stability as compared to silver. Adesto has targeted the ultralow power memory for Internet-of-Things (IoT) applications. Adesto has released products manufactured at Altis foundry[62] and entered into a 45nm foundry agreement with TowerJazz/Panasonic.[63]

Crossbar

Crossbar implements an Ag filament in amorphous Si along with a threshold switching system to achieve a diode+ReRAM.[64][65] Their system includes the use of a transistor in 1T1R or 1TNR architecture. Crossbar started producing samples at SMIC on the 40nm process in 2017.[66] The Ag filament diameter has been visualized on the scale of tens of nanometers.[67]

Programmable metallization cell

Infineon Technologies calls it conductive-bridging RAM(CBRAM), NEC has a variant called “Nanobridge” and Sony calls their version “electrolytic memory”. New research suggests CBRAM can be 3D printed[68][69]

ReRam test boards

  • Panasonic AM13L-STK2 : MN101LR05D 8-bit MCU with built in ReRAM for evaluation, USB 2.0 connector

Future applications

Compared to PRAM, ReRAM operates at a faster timescale (switching time can be less than 10 ns), while compared to MRAM, it has a simpler, smaller cell structure (less than 8F² MIM stack). A vertical 1D1R (one diode, one resistive switching device) integration can be used for crossbar memory structure to reduce the unit cell size to 4F² (F is the feature dimension).[70] Compared to flash memory and racetrack memory, a lower voltage is sufficient, and hence it can be used in low-power applications. Also, due to its relatively small access latency and high density, ReRAM is considered a promising candidate for designing caches.[71]

ITRI has shown that ReRAM is scalable below 30 nm.[72] The motion of oxygen atoms is a key phenomenon for oxide-based ReRAM;[73] one study indicated that oxygen motion may take place in regions as small as 2 nm.[74] It is believed that if a filament is responsible, it would not exhibit direct scaling with cell size.[75] Instead, the current compliance limit (set by an outside resistor, for example) could define the current-carrying capacity of the filament.[76]

A significant hurdle to realizing the potential of ReRAM is the sneak path problem that occurs in larger passive arrays. In 2010, complementary resistive switching (CRS) was introduced as a possible solution to sneak-path current interference.[77] In the CRS approach, the information storing states are pairs of high- and low-resistance states (HRS/LRS and LRS/HRS) so that the overall resistance is always high, allowing larger passive crossbar arrays.

A drawback to the initial CRS solution is the requirement for switching endurance caused by conventional destructive readout based on current measurements. A new approach for a nondestructive readout based on capacity measurement potentially lowers the requirements for both material endurance and power consumption.[78] Bi-layer structure is used to produce the nonlinearity in LRS to avoid the sneak path problem.[79] A single-layer device exhibiting a strong nonlinear conduction in LRS was reported.[80] Another bi-layer structure was introduced for bipolar ReRAM to improve the HRS and stability.[81]

Another solution to the sneak current issue is to perform read and reset operations in parallel across an entire row of cells, while using set on selected cells.[82] In this case, for a 3D-ReRAM 1TNR array, with a column of N ReRAM cells situated above a select transistor, only the intrinsic nonlinearity of the HRS is required to be sufficiently large, since the number of vertical levels N is limited (e.g., N = 8–32), and this has been shown possible for a low-current ReRAM system.[83]

Modeling of 2D and 3D caches designed with ReRAM and other non-volatile random access memories such as MRAM and PCM can be done using DESTINY[84] tool.

References

  1. ↑ U.S. Patent 6,531,371
  2. ↑ U.S. Patent 7,292,469
  3. ↑ U.S. Patent 6,867,996
  4. ↑ "MN101L ReRAM Embedded MCUs - Panasonic | Mouser". www.mouser.com. Retrieved 2016-06-08.
  5. ↑ Lee, H. Y.; Chen, P. S.; Wu, T. Y.; Chen, Y. S.; Wang, C. C.; Tzeng, P. J.; Lin, C. H.; Chen, F.; Lien, C. H.; Tsai, M. J. (2008). "Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM". 2008 IEEE International Electron Devices Meeting: 1–4. doi:10.1109/IEDM.2008.4796677.
  6. ↑ "RRAM: Trademark 003062791". euipo.europa.eu. EUIPO.
  7. ↑ Mellor, Chris (7 February 2012), Rambus drops $35m for Unity Semiconductor
  8. ↑ "the new microcontrollers with on-chip non-volatile memory ReRAM" (Press release). Panasonic. May 15, 2012. Retrieved May 16, 2012.
  9. ↑ "Next-gen storage wars: In the battle of RRAM vs 3D NAND flash, all of us are winners" (Press release). PC World. August 9, 2013. Retrieved January 28, 2014.
  10. ↑ Lamb, D R; Rundle, P C (1967). "A non-filamentary switching action in thermally grown silicon dioxide films". British Journal of Applied Physics. 18: 29. Bibcode:1967BJAP...18...29L. doi:10.1088/0508-3443/18/1/306.
  11. ↑ Park, In-Sung; Kim, Kyong-Rae; Lee, Sangsul; Ahn, Jinho (2007). "Resistance Switching Characteristics for Nonvolatile Memory Operation of Binary Metal Oxides". Japanese Journal of Applied Physics. 46 (4B): 2172. Bibcode:2007JaJAP..46.2172P. doi:10.1143/JJAP.46.2172.
  12. ↑ Mehonic, A.; Cueff, S. B.; Wojdak, M.; Hudziak, S.; Jambois, O.; Labbé, C.; Garrido, B.; Rizk, R.; Kenyon, A. J. (2012). "Resistive switching in silicon suboxide films". Journal of Applied Physics. 111 (7): 074507. Bibcode:2012JAP...111g4507M. doi:10.1063/1.3701581.
  13. ↑ Bashara, N. M.; Nielsen, P. H. (1963). "Memory effects in thin film negative resistance structures". Annual Report 1963 Conference on Electrical Insulation: 29–32. doi:10.1109/EIC.1963.7466544.
  14. ↑ Nielsen, P. H.; Bashara, N. M. (1964). "The reversible voltage-induced initial resistance in the negative resistance sandwich structure". IEEE Transactions on Electron Devices. 11 (5): 243–244. Bibcode:1964ITED...11..243N. doi:10.1109/T-ED.1964.15319. ISSN 0018-9383.
  15. ↑ Simmons, J. G.; Verderber, R. R. (August 1967). "New thin-film resistive memory". Radio and Electronic Engineer. 34 (2): 81–89. doi:10.1049/ree.1967.0069. ISSN 0033-7722.
  16. ↑ Lomax, R. W.; Simmons, J. G. (1968). "A thin film, cold cathode, alpha-numeric display panel". Radio and Electronic Engineer. 35 (5): 265–272. doi:10.1049/ree.1968.0039. ISSN 0033-7722.
  17. ↑ Dearnaley, G.; Stoneham, A. M.; Morgan, D. V. (1970). "Electrical phenomena in amorphous oxide films" (PDF). Reports on Progress in Physics. 33 (3): 1129–1191. Bibcode:1970RPPh...33.1129D. doi:10.1088/0034-4885/33/3/306. ISSN 0034-4885. [p. 1180] A thin-film resistive memory array based upon voltage-controlled negative resistance in SiO, was first proposed by Nielsen and Bashara (1964) and such a device has been described by Simmons and Verderber (1968).
  18. ↑ Jung, K. B.; Lee, J. W.; Park, Y. D.; Childress, J. R.; Pearton, S. J.; Jenson, M.; Hurst, A. T. (1 November 1997). "Electron cyclotron resonance plasma etching of materials for magneto-resistive random access memory applications". Journal of Electronic Materials. 26 (11): 1310–1313. Bibcode:1997JEMat..26.1310J. doi:10.1007/s11664-997-0076-x. ISSN 0361-5235.
  19. ↑ Chua, L. O. (2011), "Resistance switching memories are memristors", Applied Physics A, 102 (4): 765–783, Bibcode:2011ApPhA.102..765C, doi:10.1007/s00339-011-6264-9
  20. ↑ Mellor, Chris (10 October 2011), "HP and Hynix to produce the memristor goods by 2013", The Register, retrieved 2012-03-07
  21. ↑ Meuffels, P.; Soni, R. (2012), "Fundamental Issues and Problems in the Realization of Memristors", arXiv:1207.7319
  22. ↑ Di Ventra, Massimiliano; Pershin, Yuriy V. (2013). "On the physical properties of memristive, memcapacitive and meminductive systems". Nanotechnology. 24 (25): 255201. arXiv:1302.7063. Bibcode:2013Nanot..24y5201D. doi:10.1088/0957-4484/24/25/255201. PMID 23708238.
  23. ↑ Valov, I.; Linn, E.; Tappertzhofen, S.; Schmelzer, S.; van den Hurk, J.; Lentz, F.; Waser, R. (2013). "Nanobatteries in redox-based resistive switches require extension of memristor theory". Nature Communications. 4: 1771. arXiv:1303.2589. Bibcode:2013NatCo...4E1771V. doi:10.1038/ncomms2784. PMC 3644102. PMID 23612312.
  24. ↑ "the Foresight Institute » Blog Archive » Nanotechnology-based next generation memory nears mass production". Foresight.org. Retrieved 2014-08-13.
  25. ↑ Mehonic, A.; Cueff, S. B.; Wojdak, M.; Hudziak, S.; Jambois, O.; Labbé, C.; Garrido, B.; Rizk, R.; Kenyon, A. J. (2012). "Resistive switching in silicon suboxide films". Journal of Applied Physics. 111 (7): 074507. Bibcode:2012JAP...111g4507M. doi:10.1063/1.3701581.
  26. ↑ Mehonic, A.; Munde, M. S.; Ng, W. H.; Buckwell, M.; Montesi, L.; Bosman, M.; Shluger, A. L.; Kenyon, A. J. (2017). "Intrinsic resistance switching in amorphous silicon oxide for high performance SiOx ReRAM devices". Microelectronic Engineering. 178: 98–103. doi:10.1016/j.mee.2017.04.033.
  27. 1 2 Lanza, Mario (2014). "A Review on Resistive Switching in High-k Dielectrics: A Nanoscale Point of View Using Conductive Atomic Force Microscope". Materials. 7 (3): 2155–2182. Bibcode:2014Mate....7.2155L. doi:10.3390/ma7032155.
  28. ↑ Lee, D.; Seong, D. J.; Jo, I.; Xiang, F.; Dong, R.; Oh, S.; Hwang, H. (2007). "Resistance switching of copper doped MoO[sub x] films for nonvolatile memory applications". Applied Physics Letters. 90 (12): 122104. Bibcode:2007ApPhL..90l2104L. doi:10.1063/1.2715002.
  29. ↑ "Resistive switching in hafnium dioxide layers: Local phenomenon at grain boundaries". Applied Physics Letters. 101 (19): 193502. 2012-11-05. Bibcode:2012ApPhL.101s3502L. doi:10.1063/1.4765342. ISSN 0003-6951.
  30. ↑ Shi, Yuanyuan; Ji, Yanfeng; Hui, Fei; Nafria, Montserrat; Porti, Marc; Bersuker, Gennadi; Lanza, Mario (2015-04-01). "In Situ Demonstration of the Link Between Mechanical Strength and Resistive Switching in Resistive Random-Access Memories". Advanced Electronic Materials. 1 (4): n/a–n/a. doi:10.1002/aelm.201400058. ISSN 2199-160X.
  31. ↑ Lanza, Mario (2017). Conductive Atomic Force Microscopy: Applications in Nanomaterials. Berlin, Germany: Wiley-VCH. pp. 10–30. ISBN 978-3-527-34091-0.
  32. 1 2 "Advanced Engineering Materials – Wiley Online Library". Aem-journal.com. Retrieved 2014-08-13.
  33. ↑ Chen, Yu-Sheng; Wu, Tai-Yuan; Tzeng, Pei-Jer; Chen, Pang-Shiu; Lee, H. Y.; Lin, Cha-Hsin; Chen, F.; Tsai, Ming-Jinn (2009). "Forming-free HfO2 bipolar RRAM device with improved endurance and high speed operation". 2009 International Symposium on VLSI Technology, Systems, and Applications: 37–38. doi:10.1109/VTSA.2009.5159281.
  34. ↑ Balakrishnan, M.; Thermadam, S. C. P.; Mitkova, M.; Kozicki, M. N. (2006). "A Low Power Non-Volatile Memory Element Based on Copper in Deposited Silicon Oxide". 2006 7th Annual Non-Volatile Memory Technology Symposium: 104–110. doi:10.1109/NVMT.2006.378887.
  35. ↑ Sills, S.; Yasuda, S.; Strand, J.; Calderoni, A.; Aratani, K.; Johnson, A.; Ramaswamy, N. (2014). "A copper ReRAM cell for Storage Class Memory applications". 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers: 1–2. doi:10.1109/VLSIT.2014.6894368.
  36. ↑ I.V. Karpov, D. Kencke, D. Kau, S. Tang and G. Spadini, MRS Proceedings, Volume 1250, 2010
  37. ↑ V. S. S. Srinivasan et al., Punchthrough-Diode-Based Bipolar RRAM Selector by Si Epitaxy," Electron Device Letters, IEEE , vol.33, no.10, pp.1396,1398, Oct. 2012 doi: 10.1109/LED.2012.2209394
  38. ↑
  39. ↑ Waser, Rainer; Aono, Masakazu (2007). "Nanoionics-based resistive switching memories" (PDF). Nature Materials. Springer Nature. 6 (11): 833–840. Bibcode:2007NatMa...6..833W. doi:10.1038/nmat2023. ISSN 1476-4660.
  40. ↑ Pan, Chengbin; Ji, Yanfeng; Xiao, Na; Hui, Fei; Tang, Kechao; Guo, Yuzheng; Xie, Xiaoming; Puglisi, Francesco M.; Larcher, Luca (2017-01-01). "Coexistence of Grain-Boundaries-Assisted Bipolar and Threshold Resistive Switching in Multilayer Hexagonal Boron Nitride". Advanced Functional Materials: n/a–n/a. doi:10.1002/adfm.201604811. ISSN 1616-3028.
  41. ↑ Puglisi, F. M.; Larcher, L.; Pan, C.; Xiao, N.; Shi, Y.; Hui, F.; Lanza, M. (2016-12-01). "2D h-BN based RRAM devices". 2016 IEEE International Electron Devices Meeting (IEDM): 34.8.1–34.8.4. doi:10.1109/IEDM.2016.7838544.
  42. ↑ Tsunoda, K.; Kinoshita, K.; Noshiro, H.; Yamazaki, Y.; Iizuka, T.; Ito, Y.; Takahashi, A.; Okano, A.; Sato, Y.; Fukano, T.; Aoki, M.; Sugiyama, Y. (2007). "Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V". 2007 IEEE International Electron Devices Meeting. p. 767. doi:10.1109/IEDM.2007.4419060. ISBN 978-1-4244-1507-6.
  43. ↑ H-Y. Lee et al., IEDM 2010.
  44. ↑ L. Goux et al., 2012 Symp. on VLSI Tech. Dig. of Tech. Papers, 159 (2012).
  45. ↑ >
  46. ↑ Y. Y. Chen et al., IEDM 2013.
  47. ↑ C-H. Ho et al., 2016 Symposium on VLSI Technology.
  48. ↑ Wei, Z.; Kanzawa, Y.; Arita, K.; Katoh, Y.; Kawai, K.; Muraoka, S.; Mitani, S.; Fujii, S.; Katayama, K.; Iijima, M.; Mikawa, T.; Ninomiya, T.; Miyanaga, R.; Kawashima, Y.; Tsuji, K.; Himeno, A.; Okada, T.; Azuma, R.; Shimakawa, K.; Sugaya, H.; Takagi, T.; Yasuhara, R.; Horiba, K.; Kumigashira, H.; Oshima, M. (2008). "Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism". 2008 IEEE International Electron Devices Meeting: 1–4. doi:10.1109/IEDM.2008.4796676.
  49. ↑ Y. Hayakawa et al., 2015 Symposium on VLSI Technology.
  50. ↑ M-J. Lee et al., Nat. Mat. 10, 625 (2011).
  51. ↑ Panasonic ReRAM-based product description
  52. ↑ Z. Wei, IMW 2013.
  53. ↑ Fujitsu announces 4Mb ReRAM
  54. ↑ Panasonic and UMC announce ReRAM development
  55. ↑ EETimes.com – Memristors ready for prime time
  56. ↑ D. B. Strukov, Nature 453, 80 (2008).
  57. ↑ J. P. Strachan et al., IEEE Trans. Elec. Dev. 60, 2194 (2013).
  58. ↑ Comparison of Pt/TiOx/Pt vs Pt/TaOx/TaOy/Pt
  59. ↑ S. Kumar et al., ACS Nano 10, 11205 (2016).
  60. ↑ J. R. Jameson et al., IEDM 2013.
  61. ↑ D. Kanter, "Adesto Targets IoT Using CBRAM, The Linley Group Microprocessor Report, Feb 2016.
  62. ↑ Altis CBRAM for Adesto
  63. ↑ Adesto/TPsco agreement
  64. ↑ Y. Dong et al., Nano. Lett. 8, 386 (2008).
  65. ↑ S. H. Jo et al., ASPDAC 2015.
  66. ↑ Crossbar sampling 40nm at SMIC
  67. ↑ TEMs of Ag filament
  68. ↑ Fully inkjet printed flexible resistive memory -AIP Scitation
  69. ↑ Mass Producing Printed Electronics -Engineering.com
  70. ↑ Zhang, Yang; Duan, Ziqing; Li, Rui; Ku, Chieh-Jen; Reyes, Pavel I; Ashrafi, Almamun; Zhong, Jian; Lu, Yicheng (2013). "Vertically integrated ZnO-Based 1D1R structure for resistive switching". Journal of Physics D: Applied Physics. 46 (14): 145101. Bibcode:2013JPhD...46n5101Z. doi:10.1088/0022-3727/46/14/145101.
  71. ↑ "A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches", Mittal et al., TPDS, 2015.
  72. ↑ Chen, Y. S.; Lee, H. Y.; Chen, P. S.; Gu, P. Y.; Chen, C. W.; Lin, W. P.; Liu, W. H.; Hsu, Y. Y.; Sheu, S. S.; Chiang, P. C.; Chen, W. S.; Chen, F. T.; Lien, C. H.; Tsai, M. J. (2009). "Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity". 2009 IEEE International Electron Devices Meeting (IEDM): 1–4. doi:10.1109/IEDM.2009.5424411.
  73. ↑ New Non-Volatile Memory Workshop 2008, Hsinchu, Taiwan.
  74. ↑ Cen, C.; Thiel, S.; Hammerl, G.; Schneider, C. W.; Andersen, K. E.; Hellberg, C. S.; Mannhart, J.; Levy, J. (2008). "Nanoscale control of an interfacial metal–insulator transition at room temperature". Nature Materials. 7 (4): 298. Bibcode:2008NatMa...7..298C. doi:10.1038/nmat2136. PMID 18311143.
  75. ↑ I. G. Baek et al.,IEDM 2004.
  76. ↑ Lin, Chih-Yang; Wu, Chen-Yu; Wu, Chung-Yi; Hu, Chenming; Tseng, Tseung-Yuen (2007). "Bistable Resistive Switching in Al2O3 Memory Thin Films". Journal of the Electrochemical Society. 154 (9): G189. doi:10.1149/1.2750450.
  77. ↑ Linn, Eike; Rosezin, Roland; Kügeler, Carsten; Waser, Rainer (2010). "Complementary resistive switches for passive nanocrossbar memories". Nature Materials. 9 (5): 403. Bibcode:2010NatMa...9..403L. doi:10.1038/nmat2748. PMID 20400954.
  78. ↑ Tappertzhofen, S; Linn, E; Nielen, L; Rosezin, R; Lentz, F; Bruchhaus, R; Valov, I; Böttger, U; Waser, R (2011). "Capacity based nondestructive readout for complementary resistive switches". Nanotechnology. 22 (39): 395203. Bibcode:2011Nanot..22M5203T. doi:10.1088/0957-4484/22/39/395203. PMID 21891857.
  79. ↑ Joshua Yang, J.; Zhang, M.-X.; Pickett, Matthew D.; Miao, Feng; Paul Strachan, John; Li, Wen-Di; Yi, Wei; Ohlberg, Douglas A. A.; Joon Choi, Byung; Wu, Wei; Nickel, Janice H.; Medeiros-Ribeiro, Gilberto; Stanley Williams, R. (2012). "Engineering nonlinearity into memristors for passive crossbar applications". Applied Physics Letters. 100 (11): 113501. Bibcode:2012ApPhL.100k3501J. doi:10.1063/1.3693392.
  80. ↑ Mehonic, Adnan; Cueff, Sébastien; Wojdak, Maciej; Hudziak, Stephen; Labbé, Christophe; Rizk, Richard; Kenyon, Anthony J (2012). "Electrically tailored resistance switching in silicon oxide". Nanotechnology. 23 (45): 455201. Bibcode:2012Nanot..23S5201M. doi:10.1088/0957-4484/23/45/455201. PMID 23064085.
  81. ↑ Zhang, Yang; Duan, Ziqing; Li, Rui; Ku, Chieh-Jen; Reyes, Pavel; Ashrafi, Almamun; Lu, Yicheng (2012). "FeZnO-Based Resistive Switching Devices". Journal of Electronic Materials. 41 (10): 2880. Bibcode:2012JEMat..41.2880Z. doi:10.1007/s11664-012-2045-2.
  82. ↑ Yoon, Hong Sik; Baek, In-Gyu; Zhao, Jinshi; Sim, Hyunjun; Park, Min Young; Lee, Hansin; Oh, Gyu-Hwan; Shin, Jong Chan; Yeo, In-Seok; Chung, U.-In (2009). "Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications". 2009 Symposium on VLSI Technology: 26–27.
  83. ↑ Chen, F. T.; Chen, Y. S.; Wu, T. Y.; Ku, T. K. (2014). "Write Scheme Allowing Reduced LRS Nonlinearity Requirement in a 3D-RRAM Array With Selector-Less 1TNR Architecture". IEEE Electron Device Letters. 35 (2): 223–225. Bibcode:2014IEDL...35..223C. doi:10.1109/LED.2013.2294809. ISSN 0741-3106.
  84. ↑ Poremba et al., "DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches", DATE, 2015.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.