System Overview

Direct-page addressing

Many instructions offer an addressing mode that accesses 1-byte memory addresses in the "direct page". This addressing mode yields shorter bytecode which presumably executes faster. The direct page's upper byte is either 0x00 or 0x01, corresponding to the P bit in the PSW register.

The stack

The lower byte of the stack pointer is specified by the SP register; the upper byte is always 0x01. The stack pointer is set to 0x01EF on restart by the IPL ROM and grows downward.

IPL ROM

On restart, the 64-byte chunk of memory at the end of the 64KB of RAM is initialized to the contents of the IPL ROM, which is where execution starts. The code in the IPL ROM sets the stack pointer to 0x01EF, zeroes the memory from 0x0000 to 0x00EF, and then waits for data from the SNES via the input ports..

00F0h Unknown

Anomie has done some tests with this register. A document on romhacking.net describes it.

00F1h Control

• PC32 - Writing 1 in this bit will zero input for ports 2 and 3
• PC10 - Writing 1 in this bit will zero input for ports 1 and 0
• ST0-2 - These are for starting the timers.

 Warning: Writing to this register will always restart/stop all of the timers.

00F2h/00F3h DSP Registers

Writing to 00F2h sets the address of the DSP register to access. Writing to 00F3h changes the value of the register pointed to. Reading from 00F3h will return the value of the register pointed at. Writing a word to 00F2h is allowed and it can be used to simultaneously set the address and write a value to the register.

00F4h-00F7h Ports

Reading from these ports will give you the values that the SNES set at $2140-$2143. Values written to these registers will be viewable by the SNES using the same $2140-$2143. The input of these ports can be cleared using the Control register.

00FAh-00FFh Timer Settings

Registers 00FAh-00FCh are used to set the timer rate. Timers 0 & 1 have a resolution of 125 microseconds. Timer 2 has a finer resolution of ~15.6 microseconds. 00FDh-00FFh are 4-bit registers containing the timer overflow count. Here is how the timers operate.

Each timer has an internal counter which is incremented at each clock input. If it equals the number in $FA-$FC (depending on which timer you're using) the corresponding counter register is incremented and the internal counter is reset. The counter registers ($FD-$FF) are 4-bit registers and can be read only. Reading from them will cause them to reset back to zero. If you don't read the counters in the limited time frame then they will overflow and be cleared to zero as well. The timer must be stopped before setting the 00FAh-00FCh registers. To start a timer write to bits 0-2 of the Control register. To stop a timer, reset the bits. Take note that writing to the control register will restart the existing timers.

Header

• Range - This is the shift value for the data. It can be 0-12.
• Filter - This selects the filter coefficients used in the decoding process. (see table below)
• Loop -This bit marks the block as one that will be within a loop. The exact function of this bit is unknown, but some commercial spc samples that I have examined have this bit set for all blocks in the sample.
• End - This bit marks the block as the last block in the sample. The DSP channel will terminate or jump to the loop point if it reaches this block.

Data

Each block contains 8 bytes of sample data (16 signed 4-bit samples). The higher nibble in each byte contains the sample that is to be decoded before the one in the lower nibble.

Decoding Process

Here is an equation to estimate the 16-bit output of the DSP. Let y and z be the last two previously decoded samples. 'a' and 'b' are the filter coefficients selected by bits 2-3 of the header byte.

 sample = S + ay + bz
 S is the shifted data:
 S = (4-bit sample) << Range

The DSP performs this procedure using minimal basic shifting operations; output accuracy won't be perfect. It also applies Gaussian interpolation to the output.

Filter Coefficients